mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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1ab5010910
The patch takes Intel ATOM A3960 as example that hard code all Px info which is needed for Px control into Acrn HV and load it in boot process. Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Kevin Tian <kevin.tian@intel.com>
108 lines
3.5 KiB
C
108 lines
3.5 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hv_lib.h>
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#include <cpu.h>
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#include <acrn_common.h>
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#include <cpu_state_tbl.h>
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/* The table includes cpu px info of Intel A3960 SoC */
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struct cpu_px_data px_a3960[] = {
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{0x960, 0, 0xA, 0xA, 0x1800, 0x1800}, /* P0 */
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{0x8FC, 0, 0xA, 0xA, 0x1700, 0x1700}, /* P1 */
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{0x898, 0, 0xA, 0xA, 0x1600, 0x1600}, /* P2 */
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{0x834, 0, 0xA, 0xA, 0x1500, 0x1500}, /* P3 */
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{0x7D0, 0, 0xA, 0xA, 0x1400, 0x1400}, /* P4 */
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{0x76C, 0, 0xA, 0xA, 0x1300, 0x1300}, /* P5 */
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{0x708, 0, 0xA, 0xA, 0x1200, 0x1200}, /* P6 */
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{0x6A4, 0, 0xA, 0xA, 0x1100, 0x1100}, /* P7 */
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{0x640, 0, 0xA, 0xA, 0x1000, 0x1000}, /* P8 */
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{0x5DC, 0, 0xA, 0xA, 0x0F00, 0x0F00}, /* P9 */
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{0x578, 0, 0xA, 0xA, 0x0E00, 0x0E00}, /* P10 */
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{0x514, 0, 0xA, 0xA, 0x0D00, 0x0D00}, /* P11 */
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{0x4B0, 0, 0xA, 0xA, 0x0C00, 0x0C00}, /* P12 */
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{0x44C, 0, 0xA, 0xA, 0x0B00, 0x0B00}, /* P13 */
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{0x3E8, 0, 0xA, 0xA, 0x0A00, 0x0A00}, /* P14 */
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{0x384, 0, 0xA, 0xA, 0x0900, 0x0900}, /* P15 */
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{0x320, 0, 0xA, 0xA, 0x0800, 0x0800} /* P16 */
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};
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struct cpu_state_table cpu_state_tbl[] = {
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{"Intel(R) Atom(TM) Processor A3960 @ 1.90GHz", 17, px_a3960}
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};
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static int get_state_tbl_idx(char *cpuname)
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{
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int i;
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int count = ARRAY_SIZE(cpu_state_tbl);
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if (!cpuname) {
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return -1;
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}
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for (i = 0; i < count; i++) {
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if (!strcmp((cpu_state_tbl[i].model_name),
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cpuname)) {
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return i;
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}
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}
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return -1;
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}
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void load_cpu_state_data(void)
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{
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int tbl_idx;
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boot_cpu_data.px_cnt = 0;
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boot_cpu_data.px_data = NULL;
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tbl_idx = get_state_tbl_idx(boot_cpu_data.model_name);
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if (tbl_idx < 0) {
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/* The state table is not found. */
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return;
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}
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if (!((cpu_state_tbl + tbl_idx)->px_cnt)
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|| !((cpu_state_tbl + tbl_idx)->px_data)) {
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/* The state table must be wrong. */
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return;
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}
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if ((cpu_state_tbl + tbl_idx)->px_cnt > MAX_PSTATE) {
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boot_cpu_data.px_cnt = MAX_PSTATE;
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} else {
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boot_cpu_data.px_cnt = (cpu_state_tbl + tbl_idx)->px_cnt;
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}
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boot_cpu_data.px_data = (cpu_state_tbl + tbl_idx)->px_data;
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}
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