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acrn-hypervisor/hypervisor/arch/x86
Li, Fei1 1e084b08f2 hv: mmu: invalidate cached translation information for guest
Sometimes we need to invalidate cached translation information for guest
when change some bits in CR0/CR4 which related to paging. Here're two cases:
1. If there change some bits to enable/disable paging (mode) or access rights.
For CR0: PG/WP/CD/NW; For CR4: PGE/PSE/PAE/SMEP/SMAP/PKE
2. When guest using PAE paging, we should reload the PDPTE registers sometimes,
detail in SDM Vol 3 Chap 4.4.1 and Chap 4.11.1

Tracked-On: #1379
Signed-off-by: Li, Fei1 <fei1.li@intel.com>
2018-10-10 09:35:29 +08:00
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2018-10-09 13:24:04 +08:00
2018-09-29 09:24:00 +08:00
2018-09-28 16:39:36 +08:00
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