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https://github.com/projectacrn/acrn-hypervisor.git
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65e4a16e6a
There're some platforms still doesn't support 1GB large page on CPU side. Such as lakefield, TNT and EHL platforms on which have some silicon bug and this case CPU don't support 1GB large page. This patch tries to release this constrain to support more hardware platform. Note this patch doesn't release the constrain on IOMMU side. Tracked-On: #4550 Signed-off-by: Li Fei1 <fei1.li@intel.com>
123 lines
3.9 KiB
C
123 lines
3.9 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PAGE_H
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#define PAGE_H
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#include <pci_devices.h>
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#define PAGE_SHIFT 12U
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#define PAGE_SIZE (1U << PAGE_SHIFT)
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#define PAGE_MASK 0xFFFFFFFFFFFFF000UL
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/* size of the low MMIO address space: 2GB */
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#define PLATFORM_LO_MMIO_SIZE 0x80000000UL
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/* size of the high MMIO address space: 1GB */
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#define PLATFORM_HI_MMIO_SIZE 0x40000000UL
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#define PML4_PAGE_NUM(size) 1UL
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#define PDPT_PAGE_NUM(size) (((size) + PML4E_SIZE - 1UL) >> PML4E_SHIFT)
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#define PD_PAGE_NUM(size) (((size) + PDPTE_SIZE - 1UL) >> PDPTE_SHIFT)
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#define PT_PAGE_NUM(size) (((size) + PDE_SIZE - 1UL) >> PDE_SHIFT)
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/*
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* The size of the guest physical address space, covered by the EPT page table of a VM.
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* With the assumptions:
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* - The GPA of DRAM & MMIO are contiguous.
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* - Guest OS won't re-program device MMIO bars to the address not covered by
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* this EPT_ADDRESS_SPACE.
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*/
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#define EPT_ADDRESS_SPACE(size) ((size > MEM_2G) ? \
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((size) + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE) \
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: (MEM_2G + PLATFORM_LO_MMIO_SIZE + PLATFORM_HI_MMIO_SIZE))
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#define PTDEV_HI_MMIO_START ((CONFIG_UOS_RAM_SIZE > MEM_2G) ? \
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(CONFIG_UOS_RAM_SIZE + PLATFORM_LO_MMIO_SIZE) : (MEM_2G + PLATFORM_LO_MMIO_SIZE))
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#define PRE_VM_EPT_ADDRESS_SPACE(size) (PTDEV_HI_MMIO_START + PTDEV_HI_MMIO_SIZE)
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#define TOTAL_EPT_4K_PAGES_SIZE (PRE_VM_NUM*(PT_PAGE_NUM(PRE_VM_EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))*MEM_4K)) + \
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(SOS_VM_NUM*(PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_SOS_RAM_SIZE))*MEM_4K)) + \
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(MAX_POST_VM_NUM*(PT_PAGE_NUM(EPT_ADDRESS_SPACE(CONFIG_UOS_RAM_SIZE))*MEM_4K))
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#define TRUSTY_PML4_PAGE_NUM(size) (1UL)
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#define TRUSTY_PDPT_PAGE_NUM(size) (1UL)
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#define TRUSTY_PD_PAGE_NUM(size) (PD_PAGE_NUM(size))
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#define TRUSTY_PT_PAGE_NUM(size) (PT_PAGE_NUM(size))
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#define TRUSTY_PGTABLE_PAGE_NUM(size) \
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(TRUSTY_PML4_PAGE_NUM(size) + TRUSTY_PDPT_PAGE_NUM(size) + TRUSTY_PD_PAGE_NUM(size) + TRUSTY_PT_PAGE_NUM(size))
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/**
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* @brief Page tables level in IA32 paging mode
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*/
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enum _page_table_level {
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/**
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* @brief The PML4 level in the page tables
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*/
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IA32E_PML4 = 0,
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/**
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* @brief The Page-Directory-Pointer-Table level in the page tables
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*/
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IA32E_PDPT = 1,
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/**
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* @brief The Page-Directory level in the page tables
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*/
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IA32E_PD = 2,
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/**
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* @brief The Page-Table level in the page tables
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*/
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IA32E_PT = 3,
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};
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struct acrn_vm;
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struct page {
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uint8_t contents[PAGE_SIZE];
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} __aligned(PAGE_SIZE);
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union pgtable_pages_info {
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struct {
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struct page *pml4_base;
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struct page *pdpt_base;
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struct page *pd_base;
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struct page *pt_base;
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} ppt;
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struct {
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uint64_t top_address_space;
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struct page *nworld_pml4_base;
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struct page *nworld_pdpt_base;
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struct page *nworld_pd_base;
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struct page *nworld_pt_base;
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struct page *sworld_pgtable_base;
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struct page *sworld_memory_base;
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} ept;
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};
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struct memory_ops {
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union pgtable_pages_info *info;
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bool (*large_page_support)(enum _page_table_level level);
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uint64_t (*get_default_access_right)(void);
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uint64_t (*pgentry_present)(uint64_t pte);
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struct page *(*get_pml4_page)(const union pgtable_pages_info *info);
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struct page *(*get_pdpt_page)(const union pgtable_pages_info *info, uint64_t gpa);
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struct page *(*get_pd_page)(const union pgtable_pages_info *info, uint64_t gpa);
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struct page *(*get_pt_page)(const union pgtable_pages_info *info, uint64_t gpa);
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void *(*get_sworld_memory_base)(const union pgtable_pages_info *info);
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void (*clflush_pagewalk)(const void *p);
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void (*tweak_exe_right)(uint64_t *entry);
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void (*recover_exe_right)(uint64_t *entry);
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};
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extern const struct memory_ops ppt_mem_ops;
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void init_ept_mem_ops(struct memory_ops *mem_ops, uint16_t vm_id);
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void *get_reserve_sworld_memory_base(void);
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#ifdef CONFIG_LAST_LEVEL_EPT_AT_BOOT
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void reserve_buffer_for_ept_pages(void);
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#endif
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#endif /* PAGE_H */
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