Haiwei Li 2cd0edaf9c hv: pci: restore bus and memory/IO info after reset ...

After some kind of reset, such as s3, pci bridge tries to restore the
bus and memory/IO info (from 0x18 to 0x32, except for Secondary Latency
Timer 0x1b) to resume device state.

This patch is to restore these info by hypervisor.

Tracked-On: #8623
Signed-off-by: Haiwei Li <haiwei.li@intel.com>

2024-06-27 11:26:09 +08:00

..

hw_thermal.h

hv: enable thermal lvt interrupt

2024-05-16 09:40:32 +08:00

hw_timer.h

…

pci.h

hv: pci: restore bus and memory/IO info after reset

2024-06-27 11:26:09 +08:00