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https://github.com/projectacrn/acrn-hypervisor.git
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8b16be9185
Many of the license and Intel copyright headers include the "All rights reserved" string. It is not relevant in the context of the BSD-3-Clause license that the code is released under. This patch removes those strings throughout the code (hypervisor, devicemodel and misc). Tracked-On: #7254 Signed-off-by: Geoffroy Van Cutsem <geoffroy.vancutsem@intel.com>
108 lines
3.7 KiB
C
108 lines
3.7 KiB
C
/*
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2019 Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Emulate a PCI bridge: Intel Corporation Sunrise Point-LP (rev f1)
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* Assumptions:
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* 1. before hypervisor bootup, all PCI devices have been configured correctly
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* by BIOS(boot loader). It's not expected service OS change the configure;
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* 2. for ACS(Access Control Service) Capability in PCI bridge is enabled and configured
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* by BIOS to support the devices under it isolated and allocated to different VMs.
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*
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* for this emulation of vpci bridge, limitations set as following:
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* 1. all configure registers are readonly
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*
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* TODO:
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* 1. configure tool can select whether a PCI bridge is emulated or pass through
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*
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* Open:
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* 1. Service VM how to reset PCI devices under the PCI bridge
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*/
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#include <asm/guest/vm.h>
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#include <errno.h>
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#include <logmsg.h>
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#include <pci.h>
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#include "vpci_priv.h"
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static void init_vpci_bridge(struct pci_vdev *vdev)
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{
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uint32_t offset, val;
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/* read PCI config space to virtual space */
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for (offset = 0x00U; offset < 0x100U; offset += 4U) {
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val = pci_pdev_read_cfg(vdev->pdev->bdf, offset, 4U);
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pci_vdev_write_vcfg(vdev, offset, 4U, val);
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}
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/* emulated for type info */
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pci_vdev_write_vcfg(vdev, PCIR_VENDOR, 2U, 0x8086U);
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pci_vdev_write_vcfg(vdev, PCIR_DEVICE, 2U, 0x9d12U);
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pci_vdev_write_vcfg(vdev, PCIR_REVID, 1U, 0xf1U);
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pci_vdev_write_vcfg(vdev, PCIR_HDRTYPE, 1U, (PCIM_HDRTYPE_BRIDGE | PCIM_MFDEV));
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pci_vdev_write_vcfg(vdev, PCIR_CLASS, 1U, PCIC_BRIDGE);
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pci_vdev_write_vcfg(vdev, PCIR_SUBCLASS, 1U, PCIS_BRIDGE_PCI);
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vdev->parent_user = NULL;
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vdev->user = vdev;
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}
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static void deinit_vpci_bridge(__unused struct pci_vdev *vdev)
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{
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vdev->parent_user = NULL;
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vdev->user = NULL;
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}
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static int32_t read_vpci_bridge_cfg(const struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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if ((offset + bytes) <= 0x100U) {
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*val = pci_vdev_read_vcfg(vdev, offset, bytes);
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} else {
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/* just passthru read to physical device when read PCIE sapce > 0x100 */
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*val = pci_pdev_read_cfg(vdev->pdev->bdf, offset, bytes);
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}
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return 0;
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}
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static int32_t write_vpci_bridge_cfg(__unused struct pci_vdev *vdev, __unused uint32_t offset,
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__unused uint32_t bytes, __unused uint32_t val)
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{
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return 0;
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}
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const struct pci_vdev_ops vpci_bridge_ops = {
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.init_vdev = init_vpci_bridge,
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.deinit_vdev = deinit_vpci_bridge,
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.write_vdev_cfg = write_vpci_bridge_cfg,
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.read_vdev_cfg = read_vpci_bridge_cfg,
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};
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