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https://github.com/projectacrn/acrn-hypervisor.git
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00b3a28d5d
RTCT has been updated to version 2, this patch updates hypervisor RTCT parser to support both version 1 and version 2 of RTCT. Tracked-On: #6020 Signed-off-by: Yonghua Huang <yonghua.huang@intel.com> Reviewed-by: Jason CJ Chen <jason.cj.chen@intel.com>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RTCT_H
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#define RTCT_H
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#include <acpi.h>
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#include "misc_cfg.h"
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#define RTCT_ENTRY_TYPE_RTCD_LIMIT 1U
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#define RTCT_ENTRY_TYPE_RTCM_BINARY 2U
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#define RTCT_ENTRY_TYPE_WRC_L3_MASKS 3U
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#define RTCT_ENTRY_TYPE_GT_L3_MASKS 4U
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#define RTCT_ENTRY_TYPE_SOFTWARE_SRAM 5U
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#define RTCT_ENTRY_TYPE_STREAM_DATAPATH 6U
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#define RTCT_ENTRY_TYPE_TIMEAWARE_SUBSYS 7U
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#define RTCT_ENTRY_TYPE_RT_IOMMU 8U
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#define RTCT_ENTRY_TYPE_MEM_HIERARCHY_LATENCY 9U
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#define RTCT_V2_COMPATIBILITY 0U
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#define RTCT_V2_RTCD_LIMIT 1U
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#define RTCT_V2_CRL_BINARY 2U
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#define RTCT_V2_IA_WAYMASK 3U
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#define RTCT_V2_WRC_WAYMASK 4U
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#define RTCT_V2_GT_WAYMASK 5U
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#define RTCT_V2_SSRAM_WAYMASK 6U
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#define RTCT_V2_SSRAM 7U
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#define RTCT_V2_MEMORY_HIERARCHY_LATENCY 8U
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#define RTCT_V2_ERROR_LOG_ADDRESS 9U
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#if !defined(PRE_RTVM_SW_SRAM_ENABLED)
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/*
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* PRE_RTVM_SW_SRAM_BASE_GPA is for Prelaunch VM only and
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* is configured by config tool on platform that Software SRAM is detected.
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*
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* For cases that Software SRAM is not detected, we still hardcode a dummy
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* placeholder entry in vE820 table of Prelaunch VM to unify the logic
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* to initialize the vE820.
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*/
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#define PRE_RTVM_SW_SRAM_BASE_GPA 0x40080000U
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#endif
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#define PRE_RTVM_SW_SRAM_MAX_SIZE 0x00800000U
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struct rtct_entry {
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uint16_t size;
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uint16_t format;
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uint32_t type;
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uint32_t data[64];
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} __packed;
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struct rtct_entry_data_compatibility {
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uint32_t rtct_ver_major;
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uint32_t rtct_ver_minor;
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uint32_t rtcd_ver_major;
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uint32_t rtcd_ver_minor;
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} __packed;
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struct rtct_entry_data_rtcm_binary
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{
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uint64_t address;
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uint32_t size;
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} __packed;
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struct rtct_entry_data_ssram
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{
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uint32_t cache_level;
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uint64_t base;
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uint32_t ways;
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uint32_t size;
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uint32_t apic_id_0; /*only the first core is responsible for initialization of L3 mem region*/
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} __packed;
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struct rtct_entry_data_ssram_v2 {
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uint32_t cache_level;
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uint32_t cache_id;
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uint64_t base;
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uint32_t size;
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uint32_t shared;
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} __packed;
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uint64_t get_software_sram_base(void);
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uint64_t get_software_sram_size(void);
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#endif /* RTCT_H */
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