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https://github.com/projectacrn/acrn-hypervisor.git
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2fbf70780e
The bracket is required when the level of precedence of the operators is less than 13. Add the bracket to logical conjunctions. The commit applys the rule to the files under Signed-off-by: Yang, Yu-chu <yu-chu.yang@intel.com> Reviewed-by: Junjie Mao <junjie.mao@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>
363 lines
11 KiB
C
363 lines
11 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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/*
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* According to "SDM APPENDIX C VMX BASIC EXIT REASONS",
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* there are 65 Basic Exit Reasons.
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*/
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#define NR_VMX_EXIT_REASONS 65U
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static int unhandled_vmexit_handler(struct vcpu *vcpu);
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static int xsetbv_vmexit_handler(struct vcpu *vcpu);
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/* VM Dispatch table for Exit condition handling */
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static const struct vm_exit_dispatch dispatch_table[NR_VMX_EXIT_REASONS] = {
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[VMX_EXIT_REASON_EXCEPTION_OR_NMI] = {
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.handler = exception_vmexit_handler},
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[VMX_EXIT_REASON_EXTERNAL_INTERRUPT] = {
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.handler = external_interrupt_vmexit_handler},
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[VMX_EXIT_REASON_TRIPLE_FAULT] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_INIT_SIGNAL] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_STARTUP_IPI] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_IO_SMI] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_OTHER_SMI] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_INTERRUPT_WINDOW] = {
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.handler = interrupt_window_vmexit_handler},
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[VMX_EXIT_REASON_NMI_WINDOW] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_TASK_SWITCH] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_CPUID] = {
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.handler = cpuid_vmexit_handler},
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[VMX_EXIT_REASON_GETSEC] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_HLT] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_INVD] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_INVLPG] = {
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.handler = unhandled_vmexit_handler,},
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[VMX_EXIT_REASON_RDPMC] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_RDTSC] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_RSM] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMCALL] = {
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.handler = vmcall_vmexit_handler},
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[VMX_EXIT_REASON_VMCLEAR] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMLAUNCH] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMPTRLD] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMPTRST] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMREAD] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMRESUME] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMWRITE] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMXOFF] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMXON] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_CR_ACCESS] = {
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.handler = cr_access_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_DR_ACCESS] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_IO_INSTRUCTION] = {
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.handler = pio_instr_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_RDMSR] = {
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.handler = rdmsr_vmexit_handler},
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[VMX_EXIT_REASON_WRMSR] = {
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.handler = wrmsr_vmexit_handler},
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[VMX_EXIT_REASON_ENTRY_FAILURE_INVALID_GUEST_STATE] = {
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.handler = unhandled_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_ENTRY_FAILURE_MSR_LOADING] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_MWAIT] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_MONITOR_TRAP] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_MONITOR] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_PAUSE] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_TPR_BELOW_THRESHOLD] = {
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.handler = tpr_below_threshold_vmexit_handler},
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[VMX_EXIT_REASON_APIC_ACCESS] = {
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.handler = apic_access_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_VIRTUALIZED_EOI] = {
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.handler = veoi_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_GDTR_IDTR_ACCESS] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_LDTR_TR_ACCESS] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_EPT_VIOLATION] = {
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.handler = ept_violation_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_EPT_MISCONFIGURATION] = {
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.handler = ept_misconfig_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_INVEPT] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_RDTSCP] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMX_PREEMPTION_TIMER_EXPIRED] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_INVVPID] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_WBINVD] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_XSETBV] = {
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.handler = xsetbv_vmexit_handler},
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[VMX_EXIT_REASON_APIC_WRITE] = {
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.handler = apic_write_vmexit_handler,
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.need_exit_qualification = 1},
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[VMX_EXIT_REASON_RDRAND] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_INVPCID] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_VMFUNC] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_ENCLS] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_RDSEED] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_PAGE_MODIFICATION_LOG_FULL] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_XSAVES] = {
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.handler = unhandled_vmexit_handler},
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[VMX_EXIT_REASON_XRSTORS] = {
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.handler = unhandled_vmexit_handler}
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};
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int vmexit_handler(struct vcpu *vcpu)
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{
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struct vm_exit_dispatch *dispatch = NULL;
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uint16_t basic_exit_reason;
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int ret;
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if (get_cpu_id() != vcpu->pcpu_id) {
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pr_fatal("vcpu is not running on its pcpu!");
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return -EINVAL;
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}
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/* Obtain interrupt info */
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vcpu->arch_vcpu.idt_vectoring_info =
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exec_vmread32(VMX_IDT_VEC_INFO_FIELD);
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/* Filter out HW exception & NMI */
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if ((vcpu->arch_vcpu.idt_vectoring_info & VMX_INT_INFO_VALID) != 0U) {
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uint32_t vector_info = vcpu->arch_vcpu.idt_vectoring_info;
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uint32_t vector = vector_info & 0xffU;
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uint32_t type = (vector_info & VMX_INT_TYPE_MASK) >> 8U;
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uint32_t err_code = 0U;
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if (type == VMX_INT_TYPE_HW_EXP) {
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if ((vector_info & VMX_INT_INFO_ERR_CODE_VALID) != 0U)
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err_code = exec_vmread32(VMX_IDT_VEC_ERROR_CODE);
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vcpu_queue_exception(vcpu, vector, err_code);
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vcpu->arch_vcpu.idt_vectoring_info = 0U;
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} else if (type == VMX_INT_TYPE_NMI) {
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vcpu_make_request(vcpu, ACRN_REQUEST_NMI);
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vcpu->arch_vcpu.idt_vectoring_info = 0U;
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} else {
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/* No action on EXT_INT or SW exception. */
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}
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}
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/* Calculate basic exit reason (low 16-bits) */
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basic_exit_reason = (uint16_t)(vcpu->arch_vcpu.exit_reason & 0xFFFFU);
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/* Log details for exit */
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pr_dbg("Exit Reason: 0x%016llx ", vcpu->arch_vcpu.exit_reason);
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/* Ensure exit reason is within dispatch table */
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if (basic_exit_reason >= ARRAY_SIZE(dispatch_table)) {
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pr_err("Invalid Exit Reason: 0x%016llx ",
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vcpu->arch_vcpu.exit_reason);
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return -EINVAL;
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}
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/* Calculate dispatch table entry */
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dispatch = (struct vm_exit_dispatch *)
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(dispatch_table + basic_exit_reason);
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/* See if an exit qualification is necessary for this exit
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* handler
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*/
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if (dispatch->need_exit_qualification != 0U) {
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/* Get exit qualification */
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vcpu->arch_vcpu.exit_qualification =
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exec_vmread(VMX_EXIT_QUALIFICATION);
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}
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/* exit dispatch handling */
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if (basic_exit_reason == VMX_EXIT_REASON_EXTERNAL_INTERRUPT) {
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/* Handling external_interrupt
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* should disable intr
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*/
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CPU_IRQ_DISABLE();
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ret = dispatch->handler(vcpu);
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CPU_IRQ_ENABLE();
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} else {
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ret = dispatch->handler(vcpu);
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}
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return ret;
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}
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static int unhandled_vmexit_handler(struct vcpu *vcpu)
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{
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pr_fatal("Error: Unhandled VM exit condition from guest at 0x%016llx ",
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exec_vmread(VMX_GUEST_RIP));
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pr_fatal("Exit Reason: 0x%016llx ", vcpu->arch_vcpu.exit_reason);
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pr_err("Exit qualification: 0x%016llx ",
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exec_vmread(VMX_EXIT_QUALIFICATION));
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TRACE_2L(TRACE_VMEXIT_UNHANDLED, vcpu->arch_vcpu.exit_reason, 0UL);
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return 0;
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}
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int cpuid_vmexit_handler(struct vcpu *vcpu)
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{
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uint64_t rax, rbx, rcx, rdx;
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rax = vcpu_get_gpreg(vcpu, CPU_REG_RAX);
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rbx = vcpu_get_gpreg(vcpu, CPU_REG_RBX);
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rcx = vcpu_get_gpreg(vcpu, CPU_REG_RCX);
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rdx = vcpu_get_gpreg(vcpu, CPU_REG_RDX);
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guest_cpuid(vcpu, (uint32_t *)&rax, (uint32_t *)&rbx,
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(uint32_t *)&rcx, (uint32_t *)&rdx);
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vcpu_set_gpreg(vcpu, CPU_REG_RAX, rax);
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vcpu_set_gpreg(vcpu, CPU_REG_RBX, rbx);
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vcpu_set_gpreg(vcpu, CPU_REG_RCX, rcx);
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vcpu_set_gpreg(vcpu, CPU_REG_RDX, rdx);
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TRACE_2L(TRACE_VMEXIT_CPUID, (uint64_t)vcpu->vcpu_id, 0UL);
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return 0;
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}
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int cr_access_vmexit_handler(struct vcpu *vcpu)
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{
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int err = 0;
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uint64_t reg;
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int idx = VM_EXIT_CR_ACCESS_REG_IDX(vcpu->arch_vcpu.exit_qualification);
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ASSERT((idx>=0) && (idx<=15), "index out of range");
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reg = vcpu_get_gpreg(vcpu, idx);
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switch ((VM_EXIT_CR_ACCESS_ACCESS_TYPE
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(vcpu->arch_vcpu.exit_qualification) << 4) |
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VM_EXIT_CR_ACCESS_CR_NUM(vcpu->arch_vcpu.exit_qualification)) {
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case 0x00U:
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/* mov to cr0 */
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err = vcpu_set_cr0(vcpu, reg);
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break;
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case 0x04U:
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/* mov to cr4 */
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err = vcpu_set_cr4(vcpu, reg);
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break;
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case 0x08U:
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/* mov to cr8 */
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/* According to SDM 6.15 "Exception and interrupt Reference":
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*
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* set reserved bit in CR8 causes GP to guest
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*/
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if (reg & ~0xFUL) {
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pr_dbg("Invalid cr8 write operation from guest");
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vcpu_inject_gp(vcpu, 0U);
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break;
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}
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vlapic_set_cr8(vcpu->arch_vcpu.vlapic, reg);
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break;
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case 0x18U:
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/* mov from cr8 */
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reg = vlapic_get_cr8(vcpu->arch_vcpu.vlapic);
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vcpu_set_gpreg(vcpu, idx, reg);
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break;
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default:
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panic("Unhandled CR access");
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return -EINVAL;
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}
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TRACE_2L(TRACE_VMEXIT_CR_ACCESS,
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VM_EXIT_CR_ACCESS_ACCESS_TYPE
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(vcpu->arch_vcpu.exit_qualification),
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VM_EXIT_CR_ACCESS_CR_NUM
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(vcpu->arch_vcpu.exit_qualification));
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return err;
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}
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/*
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* XSETBV instruction set's the XCR0 that is used to tell for which
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* components states can be saved on a context switch using xsave.
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*/
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static int xsetbv_vmexit_handler(struct vcpu *vcpu)
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{
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int idx;
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uint64_t val64;
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val64 = exec_vmread(VMX_GUEST_CR4);
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if ((val64 & CR4_OSXSAVE) == 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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}
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idx = vcpu->arch_vcpu.cur_context;
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if (idx >= NR_WORLD) {
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return -1;
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}
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/*to access XCR0,'rcx' should be 0*/
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if (vcpu_get_gpreg(vcpu, CPU_REG_RCX) != 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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}
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val64 = (vcpu_get_gpreg(vcpu, CPU_REG_RAX) & 0xffffffffUL) |
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(vcpu_get_gpreg(vcpu, CPU_REG_RDX) << 32U);
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/*bit 0(x87 state) of XCR0 can't be cleared*/
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if ((val64 & 0x01UL) == 0UL) {
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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}
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/*XCR0[2:1] (SSE state & AVX state) can't not be
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*set to 10b as it is necessary to set both bits
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*to use AVX instructions.
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**/
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if (((val64 >> 1U) & 0x3UL) == 0x2UL) {
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vcpu_inject_gp(vcpu, 0U);
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return 0;
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}
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write_xcr(0, val64);
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return 0;
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}
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