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https://github.com/projectacrn/acrn-hypervisor.git
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3027bfab10
In the hypervisor, physical cpu id is defined as "int" or "uint32_t"
type in the hypervisor. So there are some sign conversion issues
about physical cpu id (pcpu_id) reported by static analysis tool.
Sign conversion violates the rules of MISRA C:2012.
In this patch, define physical cpu id as "uint16_t" type for all
modules in the hypervisor and change related codes. The valid
range of pcpu_id is 0~65534, INVALID_PCPU_ID is defined to the
invalid pcpu_id for error detection, BROADCAST_PCPU_ID is
broadcast pcpu_id used to notify all valid pcpu.
The type of pcpu_id in the struct vcpu and vcpu_id is "int" type,
this will be fixed in another patch.
V1-->V2:
* Change the type of pcpu_id from uint32_t to uint16_t;
* Define INVALID_PCPU_ID for error detection;
* Define BROADCAST_PCPU_ID to notify all valid pcpu.
V2-->V3:
* Update comments for INVALID_PCPU_ID and BROADCAST_PCPU_ID;
* Update addtional pcpu_id;
* Convert hexadecimals to unsigned to meet the type of pcpu_id;
* Clean up for MIN_PCPU_ID and MAX_PCPU_ID, they will be
defined by configuration.
Note: fix bug in the init_lapic(), the pcpu_id shall be less than 8,
this is constraint by implement in the init_lapic().
Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
279 lines
7.8 KiB
C
279 lines
7.8 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _VCPU_H_
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#define _VCPU_H_
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#define ACRN_VCPU_MMIO_COMPLETE (0)
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/* Size of various elements within the VCPU structure */
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#define REG_SIZE 8
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/* Number of GPRs saved / restored for guest in VCPU structure */
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#define NUM_GPRS 15
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#define GUEST_STATE_AREA_SIZE 512
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/* Indexes of GPRs saved / restored for guest */
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#define VMX_MACHINE_T_GUEST_RAX_INDEX 0
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#define VMX_MACHINE_T_GUEST_RBX_INDEX 1
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#define VMX_MACHINE_T_GUEST_RCX_INDEX 2
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#define VMX_MACHINE_T_GUEST_RDX_INDEX 3
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#define VMX_MACHINE_T_GUEST_RBP_INDEX 4
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#define VMX_MACHINE_T_GUEST_RSI_INDEX 5
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#define VMX_MACHINE_T_GUEST_R8_INDEX 6
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#define VMX_MACHINE_T_GUEST_R9_INDEX 7
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#define VMX_MACHINE_T_GUEST_R10_INDEX 8
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#define VMX_MACHINE_T_GUEST_R11_INDEX 9
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#define VMX_MACHINE_T_GUEST_R12_INDEX 10
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#define VMX_MACHINE_T_GUEST_R13_INDEX 11
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#define VMX_MACHINE_T_GUEST_R14_INDEX 12
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#define VMX_MACHINE_T_GUEST_R15_INDEX 13
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#define VMX_MACHINE_T_GUEST_RDI_INDEX 14
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/* Offsets of GPRs for guest within the VCPU data structure */
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#define VMX_MACHINE_T_GUEST_RAX_OFFSET (VMX_MACHINE_T_GUEST_RAX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RBX_OFFSET (VMX_MACHINE_T_GUEST_RBX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RCX_OFFSET (VMX_MACHINE_T_GUEST_RCX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RDX_OFFSET (VMX_MACHINE_T_GUEST_RDX_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RBP_OFFSET (VMX_MACHINE_T_GUEST_RBP_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RSI_OFFSET (VMX_MACHINE_T_GUEST_RSI_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_RDI_OFFSET (VMX_MACHINE_T_GUEST_RDI_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R8_OFFSET (VMX_MACHINE_T_GUEST_R8_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R9_OFFSET (VMX_MACHINE_T_GUEST_R9_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R10_OFFSET (VMX_MACHINE_T_GUEST_R10_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R11_OFFSET (VMX_MACHINE_T_GUEST_R11_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R12_OFFSET (VMX_MACHINE_T_GUEST_R12_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R13_OFFSET (VMX_MACHINE_T_GUEST_R13_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R14_OFFSET (VMX_MACHINE_T_GUEST_R14_INDEX*REG_SIZE)
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#define VMX_MACHINE_T_GUEST_R15_OFFSET (VMX_MACHINE_T_GUEST_R15_INDEX*REG_SIZE)
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/* Hard-coded offset of cr2 in struct run_context!! */
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#define VMX_MACHINE_T_GUEST_CR2_OFFSET (128)
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/* Hard-coded offset of cr2 in struct run_context!! */
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#define VMX_MACHINE_T_GUEST_SPEC_CTRL_OFFSET (192)
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/*sizes of various registers within the VCPU data structure */
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#define VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE GUEST_STATE_AREA_SIZE
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#ifndef ASSEMBLER
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enum vcpu_state {
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VCPU_INIT,
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VCPU_RUNNING,
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VCPU_PAUSED,
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VCPU_ZOMBIE,
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VCPU_UNKNOWN_STATE,
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};
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struct cpu_regs {
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uint64_t rax;
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uint64_t rbx;
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uint64_t rcx;
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uint64_t rdx;
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uint64_t rbp;
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uint64_t rsi;
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uint64_t r8;
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uint64_t r9;
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uint64_t r10;
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uint64_t r11;
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uint64_t r12;
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uint64_t r13;
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uint64_t r14;
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uint64_t r15;
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uint64_t rdi;
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};
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struct segment {
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uint64_t selector;
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uint64_t base;
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uint64_t limit;
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uint64_t attr;
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};
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struct run_context {
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/* Contains the guest register set.
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* NOTE: This must be the first element in the structure, so that the offsets
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* in vmx_asm.S match
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*/
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union {
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struct cpu_regs regs;
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uint64_t longs[NUM_GPRS];
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} guest_cpu_regs;
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/** The guests CR registers 0, 2, 3 and 4. */
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uint64_t cr0;
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/* VMX_MACHINE_T_GUEST_CR2_OFFSET =
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* offsetof(struct run_context, cr2) = 128
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*/
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uint64_t cr2;
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uint64_t cr3;
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uint64_t cr4;
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uint64_t rip;
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uint64_t rsp;
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uint64_t rflags;
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uint64_t dr7;
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uint64_t tsc_offset;
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/* MSRs */
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/* VMX_MACHINE_T_GUEST_SPEC_CTRL_OFFSET =
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* offsetof(struct run_context, ia32_spec_ctrl) = 192
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*/
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uint64_t ia32_spec_ctrl;
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uint64_t ia32_star;
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uint64_t ia32_lstar;
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uint64_t ia32_fmask;
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uint64_t ia32_kernel_gs_base;
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uint64_t ia32_pat;
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uint64_t ia32_efer;
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uint64_t ia32_sysenter_cs;
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uint64_t ia32_sysenter_esp;
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uint64_t ia32_sysenter_eip;
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uint64_t ia32_debugctl;
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uint64_t vmx_cr0;
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uint64_t vmx_cr4;
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/* segment registers */
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struct segment cs;
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struct segment ss;
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struct segment ds;
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struct segment es;
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struct segment fs;
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struct segment gs;
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struct segment tr;
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struct segment idtr;
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struct segment ldtr;
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struct segment gdtr;
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/* The 512 bytes area to save the FPU/MMX/SSE states for the guest */
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uint64_t
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fxstore_guest_area[VMX_CPU_S_FXSAVE_GUEST_AREA_SIZE / sizeof(uint64_t)]
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__aligned(16);
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};
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/* 2 worlds: 0 for Normal World, 1 for Secure World */
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#define NR_WORLD 2
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#define NORMAL_WORLD 0
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#define SECURE_WORLD 1
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struct event_injection_info {
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uint32_t intr_info;
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uint32_t error_code;
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};
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struct vcpu_arch {
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int cur_context;
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struct run_context contexts[NR_WORLD];
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/* A pointer to the VMCS for this CPU. */
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void *vmcs;
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int vpid;
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/* Holds the information needed for IRQ/exception handling. */
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struct {
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/* The number of the exception to raise. */
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uint32_t exception;
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/* The error number for the exception. */
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int error;
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} exception_info;
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uint8_t lapic_mask;
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uint32_t irq_window_enabled;
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uint32_t nrexits;
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/* Auxiliary TSC value */
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uint64_t msr_tsc_aux;
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/* VCPU context state information */
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uint32_t exit_reason;
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uint32_t idt_vectoring_info;
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uint64_t exit_qualification;
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uint32_t inst_len;
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/* Information related to secondary / AP VCPU start-up */
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uint8_t cpu_mode;
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uint8_t nr_sipi;
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uint32_t sipi_vector;
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/* interrupt injection information */
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uint64_t pending_req;
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bool inject_event_pending;
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struct event_injection_info inject_info;
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/* per vcpu lapic */
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void *vlapic;
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};
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struct vm;
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struct vcpu {
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int pcpu_id; /* Physical CPU ID of this VCPU */
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int vcpu_id; /* virtual identifier for VCPU */
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struct vcpu_arch arch_vcpu;
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/* Architecture specific definitions for this VCPU */
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struct vm *vm; /* Reference to the VM this VCPU belongs to */
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void *entry_addr; /* Entry address for this VCPU when first started */
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/* State of this VCPU before suspend */
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volatile enum vcpu_state prev_state;
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volatile enum vcpu_state state; /* State of this VCPU */
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/* State of debug request for this VCPU */
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volatile enum vcpu_state dbg_req_state;
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unsigned long sync; /*hold the bit events*/
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struct vlapic *vlapic; /* per vCPU virtualized LAPIC */
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struct list_head run_list; /* inserted to schedule runqueue */
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unsigned long pending_pre_work; /* any pre work pending? */
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bool launched; /* Whether the vcpu is launched on target pcpu */
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unsigned int paused_cnt; /* how many times vcpu is paused */
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int running; /* vcpu is picked up and run? */
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int ioreq_pending; /* ioreq is ongoing or not? */
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struct vhm_request req; /* used by io/ept emulation */
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struct mem_io mmio; /* used by io/ept emulation */
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/* save guest msr tsc aux register.
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* Before VMENTRY, save guest MSR_TSC_AUX to this fields.
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* After VMEXIT, restore this fields to guest MSR_TSC_AUX.
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* This is only temperary workaround. Once MSR emulation
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* is enabled, we should remove this fields and related
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* code.
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*/
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uint64_t msr_tsc_aux_guest;
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uint64_t *guest_msrs;
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#ifdef CONFIG_MTRR_ENABLED
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struct mtrr_state mtrr;
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#endif
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};
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#define is_vcpu_bsp(vcpu) ((vcpu)->vcpu_id == 0)
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/* do not update Guest RIP for next VM Enter */
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#define VCPU_RETAIN_RIP(vcpu) ((vcpu)->arch_vcpu.inst_len = 0)
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/* External Interfaces */
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struct vcpu* get_ever_run_vcpu(uint16_t pcpu_id);
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int create_vcpu(uint16_t cpu_id, struct vm *vm, struct vcpu **rtn_vcpu_handle);
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int start_vcpu(struct vcpu *vcpu);
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int shutdown_vcpu(struct vcpu *vcpu);
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void destroy_vcpu(struct vcpu *vcpu);
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void reset_vcpu(struct vcpu *vcpu);
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void pause_vcpu(struct vcpu *vcpu, enum vcpu_state new_state);
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void resume_vcpu(struct vcpu *vcpu);
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void schedule_vcpu(struct vcpu *vcpu);
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int prepare_vcpu(struct vm *vm, uint16_t pcpu_id);
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void request_vcpu_pre_work(struct vcpu *vcpu, int pre_work_id);
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#endif
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#endif
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