mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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7a3a539b17
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
440 lines
10 KiB
C
440 lines
10 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hypervisor.h>
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#include <hv_lib.h>
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#include <acrn_common.h>
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#include <hv_arch.h>
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#include <hv_debug.h>
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/* Register offsets */
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#define IOAPIC_REGSEL_OFFSET 0
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#define IOAPIC_WINSWL_OFFSET 0x10
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/* IOAPIC Redirection Table (RTE) Entry structure */
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struct ioapic_rte {
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uint32_t lo_32;
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uint32_t hi_32;
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} ioapic_rte;
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struct gsi_table {
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uint8_t ioapic_id;
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uint8_t pin;
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uint64_t addr;
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};
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static struct gsi_table gsi_table[NR_MAX_GSI];
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static int nr_gsi;
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static spinlock_t ioapic_lock;
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/*
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* the irq to ioapic pin mapping should extract from ACPI MADT table
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* hardcoded here
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*/
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uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
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2, /* IRQ0*/
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1, /* IRQ1*/
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0, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */
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3, /* IRQ3*/
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4, /* IRQ4*/
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5, /* IRQ5*/
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6, /* IRQ6*/
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7, /* IRQ7*/
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8, /* IRQ8*/
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9 | IOAPIC_RTE_TRGRLVL, /* IRQ9*/
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10, /* IRQ10*/
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11, /* IRQ11*/
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12, /* IRQ12*/
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13, /* IRQ13*/
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14, /* IRQ14*/
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15, /* IRQ15*/
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};
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static uint64_t map_ioapic(
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uint64_t ioapic_paddr)
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{
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/* At some point we may need to translate this paddr to a vaddr.
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* 1:1 mapping for now.
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*/
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return (vaddr_t) ioapic_paddr;
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}
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static inline uint32_t
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ioapic_read_reg32(const uint64_t ioapic_base, const uint8_t offset)
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{
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uint32_t v;
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spinlock_rflags;
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spinlock_irqsave_obtain(&ioapic_lock);
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/* Write IOREGSEL */
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*(uint32_t *)(ioapic_base) = offset;
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/* Read IOWIN */
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v = *(uint32_t *)(ioapic_base + IOAPIC_WINSWL_OFFSET);
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spinlock_irqrestore_release(&ioapic_lock);
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return v;
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}
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static inline void
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ioapic_write_reg32(const uint64_t ioapic_base,
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const uint8_t offset, const uint32_t value)
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{
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spinlock_rflags;
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spinlock_irqsave_obtain(&ioapic_lock);
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/* Write IOREGSEL */
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*(uint32_t *)(ioapic_base) = offset;
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/* Write IOWIN */
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*(uint32_t *)(ioapic_base + IOAPIC_WINSWL_OFFSET) = value;
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spinlock_irqrestore_release(&ioapic_lock);
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}
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static inline uint64_t
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get_ioapic_base(int apic_id)
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{
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uint64_t addr = -1UL;
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/* should extract next ioapic from ACPI MADT table */
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if (apic_id == 0)
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addr = DEFAULT_IO_APIC_BASE;
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else if (apic_id == 1)
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addr = 0xfec3f000;
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else if (apic_id == 2)
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addr = 0xfec7f000;
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else
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ASSERT(apic_id <= 2, "ACPI MADT table missing");
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return addr;
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}
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static inline void
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ioapic_get_rte_entry(uint64_t ioapic_addr,
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int pin, struct ioapic_rte *rte)
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{
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rte->lo_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x10);
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rte->hi_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x11);
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}
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static inline void
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ioapic_set_rte_entry(uint64_t ioapic_addr,
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int pin, struct ioapic_rte *rte)
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{
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ioapic_write_reg32(ioapic_addr, pin*2 + 0x10, rte->lo_32);
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ioapic_write_reg32(ioapic_addr, pin*2 + 0x11, rte->hi_32);
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}
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static inline struct ioapic_rte
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create_rte_for_legacy_irq(int irq, int vr)
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{
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struct ioapic_rte rte = {0, 0};
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/* Legacy IRQ 0-15 setup, default masked
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* are actually defined in either MPTable or ACPI MADT table
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* before we have ACPI table parsing in HV we use common hardcode
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*/
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rte.lo_32 |= IOAPIC_RTE_INTMSET;
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rte.lo_32 |= (legacy_irq_to_pin[irq] & IOAPIC_RTE_TRGRLVL);
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rte.lo_32 |= DEFAULT_DEST_MODE;
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rte.lo_32 |= DEFAULT_DELIVERY_MODE;
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rte.lo_32 |= (IOAPIC_RTE_INTVEC & vr);
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/* FIXME: Fixed to active Low? */
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rte.lo_32 |= IOAPIC_RTE_INTALO;
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/* Dest field: legacy irq fixed to CPU0 */
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rte.hi_32 |= 1 << 24;
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return rte;
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}
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static inline struct ioapic_rte
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create_rte_for_gsi_irq(int irq, int vr)
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{
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struct ioapic_rte rte = {0, 0};
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if (irq < NR_LEGACY_IRQ)
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return create_rte_for_legacy_irq(irq, vr);
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/* irq default masked, level trig */
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rte.lo_32 |= IOAPIC_RTE_INTMSET;
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rte.lo_32 |= IOAPIC_RTE_TRGRLVL;
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rte.lo_32 |= DEFAULT_DEST_MODE;
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rte.lo_32 |= DEFAULT_DELIVERY_MODE;
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rte.lo_32 |= (IOAPIC_RTE_INTVEC & vr);
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/* FIXME: Fixed to active Low? */
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rte.lo_32 |= IOAPIC_RTE_INTALO;
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/* Dest field */
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rte.hi_32 |= ALL_CPUS_MASK << 24;
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return rte;
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}
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static void ioapic_set_routing(int gsi, int vr)
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{
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uint64_t addr;
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struct ioapic_rte rte;
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addr = gsi_table[gsi].addr;
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rte = create_rte_for_gsi_irq(gsi, vr);
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ioapic_set_rte_entry(addr, gsi_table[gsi].pin, &rte);
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if (rte.lo_32 & IOAPIC_RTE_TRGRMOD)
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update_irq_handler(gsi, handle_level_interrupt_common);
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else
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update_irq_handler(gsi, common_handler_edge);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%d rte:%x",
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gsi, gsi_table[gsi].pin,
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rte.lo_32);
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}
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void ioapic_get_rte(int irq, uint64_t *rte)
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{
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uint64_t addr;
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struct ioapic_rte _rte;
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if (!irq_is_gsi(irq))
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return;
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addr = gsi_table[irq].addr;
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ioapic_get_rte_entry(addr, gsi_table[irq].pin, &_rte);
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*rte = _rte.hi_32;
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*rte = *rte << 32 | _rte.lo_32;
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}
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void ioapic_set_rte(int irq, uint64_t raw_rte)
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{
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uint64_t addr;
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struct ioapic_rte rte;
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if (!irq_is_gsi(irq))
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return;
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addr = gsi_table[irq].addr;
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rte.lo_32 = raw_rte;
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rte.hi_32 = raw_rte >> 32;
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ioapic_set_rte_entry(addr, gsi_table[irq].pin, &rte);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%d rte:%x",
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irq, gsi_table[irq].pin,
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rte.lo_32);
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}
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int irq_gsi_num(void)
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{
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return nr_gsi;
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}
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bool irq_is_gsi(int irq)
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{
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return irq < nr_gsi;
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}
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int irq_to_pin(int irq)
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{
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if (irq_is_gsi(irq))
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return gsi_table[irq].pin;
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else
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return -1;
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}
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int pin_to_irq(int pin)
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{
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int i;
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if (pin < 0)
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return IRQ_INVALID;
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for (i = 0; i < nr_gsi; i++) {
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if (gsi_table[i].pin == (uint8_t) pin)
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return i;
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}
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return IRQ_INVALID;
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}
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void
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irq_gsi_mask_unmask(int irq, bool mask)
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{
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uint64_t addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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if (!irq_is_gsi(irq))
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return;
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask)
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rte.lo_32 |= IOAPIC_RTE_INTMSET;
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else
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rte.lo_32 &= ~IOAPIC_RTE_INTMASK;
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ioapic_set_rte_entry(addr, pin, &rte);
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dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%d rte:%x",
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irq, pin, rte.lo_32);
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}
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void setup_ioapic_irq(void)
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{
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int ioapic_id;
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int gsi;
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int vr;
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spinlock_init(&ioapic_lock);
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for (ioapic_id = 0, gsi = 0; ioapic_id < NR_IOAPICS; ioapic_id++) {
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int pin;
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int max_pins;
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int version;
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uint64_t addr;
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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version = ioapic_read_reg32(addr, IOAPIC_VER);
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max_pins = (version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT;
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dev_dbg(ACRN_DBG_IRQ, "IOAPIC version: %x", version);
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ASSERT(max_pins > NR_LEGACY_IRQ,
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"Legacy IRQ num > total GSI");
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for (pin = 0; pin < max_pins; pin++) {
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gsi_table[gsi].ioapic_id = ioapic_id;
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gsi_table[gsi].addr = addr;
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if (gsi < NR_LEGACY_IRQ)
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gsi_table[gsi].pin =
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legacy_irq_to_pin[gsi] & 0xff;
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else
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gsi_table[gsi].pin = pin;
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/* pinned irq before use it */
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if (irq_mark_used(gsi) < 0) {
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pr_err("failed to alloc IRQ[%d]", gsi);
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gsi++;
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continue;
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}
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/* assign vector for this GSI
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* for legacy irq, reserved vector and never free
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*/
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if (gsi < NR_LEGACY_IRQ) {
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vr = irq_desc_alloc_vector(gsi, false);
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if (vr < 0) {
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pr_err("failed to alloc VR");
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gsi++;
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continue;
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}
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} else
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vr = 0; /* not to allocate VR right now */
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ioapic_set_routing(gsi, vr);
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gsi++;
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}
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}
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/* system max gsi numbers */
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nr_gsi = gsi;
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ASSERT(nr_gsi < NR_MAX_GSI, "GSI table overflow");
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}
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void dump_ioapic(void)
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{
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int irq;
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for (irq = 0; irq < nr_gsi; irq++) {
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uint64_t addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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ioapic_get_rte_entry(addr, pin, &rte);
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dev_dbg(ACRN_DBG_IRQ, "DUMP: irq:%d pin:%d rte:%x",
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irq, pin, rte.lo_32);
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}
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}
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void get_rte_info(struct ioapic_rte *rte, bool *mask, bool *irr,
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bool *phys, int *delmode, bool *level, int *vector, uint32_t *dest)
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{
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*mask = ((rte->lo_32 & IOAPIC_RTE_INTMASK) == IOAPIC_RTE_INTMSET);
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*irr = ((rte->lo_32 & IOAPIC_RTE_REM_IRR) == IOAPIC_RTE_REM_IRR);
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*phys = ((rte->lo_32 & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
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*delmode = rte->lo_32 & IOAPIC_RTE_DELMOD;
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*level = rte->lo_32 & IOAPIC_RTE_TRGRLVL ? true : false;
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*vector = rte->lo_32 & IOAPIC_RTE_INTVEC;
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*dest = rte->hi_32 >> APIC_ID_SHIFT;
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}
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int get_ioapic_info(char *str, int str_max_len)
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{
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int irq, len, size = str_max_len;
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len = snprintf(str, size,
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"\r\nIRQ\tPIN\tRTE.HI32\tRTE.LO32\tVEC\tDST\tDM\tTM\tDELM\tIRR\tMASK");
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size -= len;
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str += len;
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for (irq = 0; irq < nr_gsi; irq++) {
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uint64_t addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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bool irr, phys, level, mask;
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int delmode, vector;
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uint32_t dest;
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ioapic_get_rte_entry(addr, pin, &rte);
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get_rte_info(&rte, &mask, &irr, &phys, &delmode, &level,
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&vector, &dest);
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len = snprintf(str, size, "\r\n%03d\t%03d\t0x%08X\t0x%08X\t",
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irq, pin, rte.hi_32, rte.lo_32);
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size -= len;
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str += len;
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len = snprintf(str, size, "0x%02X\t0x%02X\t%s\t%s\t%d\t%d\t%d",
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vector, dest, phys ? "phys" : "logic",
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level ? "level" : "edge", delmode >> 8, irr, mask);
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size -= len;
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str += len;
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if (size < 2) {
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pr_err("\r\nsmall buffer for ioapic dump");
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return -1;
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}
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}
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snprintf(str, size, "\r\n");
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return 0;
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}
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