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1949c0b52f
Use tp register to hold the current logical CPU ID. This follows the same design as x86 which uses MSR_IA32_SYSENTER_CS for the same purpose. riscv uses SBI HSM to start the APs. Tracked-On: #8791 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
22 lines
382 B
C
22 lines
382 B
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_PERCPU_H
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#define RISCV_PERCPU_H
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#include <types.h>
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#include <asm/page.h>
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struct per_cpu_arch {
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uint32_t hart_id;
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} __aligned(PAGE_SIZE); /* per_cpu_region size aligned with PAGE_SIZE */
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#endif /* RISCV_PERCPU_H */
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