Wei6 Zhang a26773314d misc: add the CONFIG_SERIAL_REG_WIDTH ...

Tracked-On: #8721
Signed-off-by: Wei6 Zhang <wei6.zhang@intel.com>

2025-09-05 12:31:42 +08:00

..

lib

misc: add the CONFIG_SERIAL_REG_WIDTH

2025-09-05 12:31:42 +08:00

bdf.py

misc: rename common.py to avoid private library conflict

2022-11-14 12:03:51 +08:00

board_capability.py

misc: rename common.py to avoid private library conflict

2022-11-14 12:03:51 +08:00

clos.py

misc: rename common.py to avoid private library conflict

2022-11-14 12:03:51 +08:00

cpu_affinity.py

misc: rename common.py to avoid private library conflict

2022-11-14 12:03:51 +08:00

cpu_freq.py

misc: rename common.py to avoid private library conflict

2022-11-14 12:03:51 +08:00

gpa.py

misc: fix invalid escape sequence in python 3.12

2024-05-09 20:58:21 +08:00

guest_flags.py

hv: add GUEST_FLAG_STATELESS flag

2024-07-30 09:26:50 +08:00

hv_ram.py

config_tools: remove ivshmem size from hv_ram_size

2024-06-28 10:00:41 +08:00

intx.py

vUART: change S5 vUART resource

2024-07-15 15:27:12 +08:00

main.py

misc: Bandit scan issue for lxml

2025-08-20 10:20:20 +08:00

memory_allocator.py

misc: rename common.py to avoid private library conflict

2022-11-14 12:03:51 +08:00

pio.py

misc: rename common.py to avoid private library conflict

2022-11-14 12:03:51 +08:00

s5_vuart.py

vUART: change S5 vUART resource

2024-07-15 15:27:12 +08:00