mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2025-11-20 12:05:39 +00:00
fc495b946a
This patch implements interrupt initialization and the basic exception/interrupt handling flow on RISC-V. init_interrupt() needs to be invoked during CPU initialization to set up the trap vector and enable the interrupt. RISC-V exception and interrupt handling includes: - Saving and restoring CPU registers around traps - Implementing handlers for: - Supervisor software interrupt - Supervisor timer interrupt - Halting the CPU for all other interrupts and exceptions ------ TODOs: 1. add support for registering interrupt handlers via request_irq() and further adoption of the common IRQ framework. 2. add support for external interrupt. Tracked-On: #8813 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: Shiqing Gao <shiqing.gao@intel.com> Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
51 lines
1.5 KiB
C
51 lines
1.5 KiB
C
/*
|
|
* Copyright (C) 2023-2025 Intel Corporation.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*
|
|
* Authors:
|
|
* Haicheng Li <haicheng.li@intel.com>
|
|
*/
|
|
|
|
#include <asm/trap.h>
|
|
#include <cpu.h>
|
|
#include <types.h>
|
|
|
|
static void init_interrupt_arch(__unused uint16_t pcpu_id)
|
|
{
|
|
uint64_t addr = (uint64_t)&strap_handler;
|
|
|
|
/*
|
|
* According to RISC-V Privileged Architecture
|
|
* 12.1.2. Supervisor Trap Vector Base Address (stvec) Register:
|
|
* The BASE field in stvec is a field that can hold any valid virtual
|
|
* or physical address, subject to the following alignment constraints:
|
|
* the address must be ``4-byte aligned``, and MODE settings other than
|
|
* Direct might impose additional alignment constraints on the
|
|
* value in the BASE field.
|
|
*/
|
|
cpu_csr_write(stvec, (addr | TRAP_VECTOR_MODE_DIRECT));
|
|
|
|
cpu_csr_write(sie, (IP_IE_SSI | IP_IE_STI | IP_IE_SEI));
|
|
}
|
|
|
|
/*
|
|
* TODO:
|
|
* This is the first step toward aligning with the common IRQ framework.
|
|
* For simplicity in this patchset, which focuses only on initialization,
|
|
* init_interrupt() is defined directly in arch/riscv/irq.c.
|
|
*
|
|
* Because interrupt handler registration via request_irq() is not yet
|
|
* implemented for RISC-V, fully aligning with the framework would require
|
|
* adding a few empty arch-specific functions as placeholders.
|
|
*
|
|
* Once request_irq() support is introduced, we can complete the integration
|
|
* with the common IRQ framework.
|
|
*/
|
|
void init_interrupt(uint16_t pcpu_id)
|
|
{
|
|
init_interrupt_arch(pcpu_id);
|
|
|
|
CPU_IRQ_ENABLE_ON_CONFIG();
|
|
}
|