acrn-hypervisor

mirror of https://github.com/projectacrn/acrn-hypervisor.git synced 2025-11-13 17:34:12 +00:00

Files

hangliu1 3d57581eb0 hv: riscv: page number calculate

this patch calculate riscv static pages number for page pool.
riscv donot need to map guest memory. use link script address
label to map code size.
For risc-v:
1) if the platform doesn't support PCIe devices
   The address space layout for risc-v is like

  |      |
  | MMIO |
  |      |
  | ...  |
  |      |
  | RAM  |
  |      |

For all its address space, one 1GB page table is enough which cover 512G
For MMIO or RAM, if its start address and end address is 1G aligned, there's no 2M
or 4K page table is needed. if their address are not 1G aligned, two 2M page table
is enough for MMIO or RAM. The issue here is that if we neetid 4K page entries for
different page attributes. So we need to reserve enough 4K page tables for that requirement.

2) if the platform support PCI devices, for the low MMIO range, another two 2MB page
table may needed. for the high MMIO range, its depends on the max physical address bits of
the platform and the high MMIO range reserved by the BIOS.

Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Fei Li <fei1.li@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>

2025-10-21 14:14:55 +08:00

guest

vuart: add dummy vuart for risc-v

2025-10-14 14:45:12 +08:00

lib

hv: multi-arch add RISC-V bits library implementation

2025-09-22 10:52:06 +08:00

cpu.h

hv: riscv: add riscv memory interface

2025-10-21 14:14:55 +08:00

init.h

hv: risc-v: add C entry function of BSP and APs