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https://github.com/projectacrn/acrn-hypervisor.git
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52e7919d9f
Add hypervisor pagetable manipulate interface to riscv arch directory, which is needed by the common interface, and add riscv ppt pgtable structure implementation. Tracked-On: #8831 Signed-off-by: Haicheng Li <haicheng.li@intel.com> Co-developed-by: hangliu1 <hang1.liu@intel.com> Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
32 lines
871 B
C
32 lines
871 B
C
/*
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* Copyright (C) 2023-2025 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef __RISCV_MM_COMMON_H__
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#define __RISCV_MM_COMMON_H__
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#include <asm/pgtable.h>
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#define PGTL3_SHIFT VPN3_SHIFT
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#define PGTL3_SIZE (1UL << PGTL3_SHIFT)
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#define PGTL3_MASK (~(PGTL3_SIZE - 1UL))
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#define PTRS_PER_PGTL3E PTRS_PER_VPN3
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#define PGTL2_SHIFT VPN2_SHIFT
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#define PGTL2_SIZE (1UL << PGTL2_SHIFT)
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#define PGTL2_MASK (~(PGTL2_SIZE - 1UL))
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#define PTRS_PER_PGTL2E PTRS_PER_VPN2
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#define PGTL1_SHIFT VPN1_SHIFT
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#define PGTL1_SIZE (1UL << PGTL1_SHIFT)
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#define PGTL1_MASK (~(PGTL1_SIZE - 1UL))
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#define PTRS_PER_PGTL1E PTRS_PER_VPN1
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#define PGTL0_SHIFT PTE_SHIFT
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#define PGTL0_SIZE (1UL << PGTL0_SHIFT)
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#define PGTL0_MASK (~(PGTL0_SIZE - 1UL))
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#define PTRS_PER_PGTL0E PTRS_PER_PTE
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#define PAGE_PFN_OFFSET 10UL
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#endif /*__RISCV_MM_COMMON_H__ */
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