mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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cfc3811a0a
There are multiple helpers for collecting info to be printed on the ACRN uart
console. They are unreachable code in release builds in which the uart console
is removed.
To define a precise boundary for safety-related activities, this patch wraps the
declarations and definitions to these helpers with "#ifdef HV_DEBUG" so that
these unreachable APIs will be dropped in release builds.
v1 -> v2:
* Fix coding style: no empty lines between #ifdef and the wrapped code.
* Also drop get_rte_info() in ioapic.c, which is solely used by
get_ioapic_info().
Signed-off-by: Junjie Mao <junjie.mao@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
474 lines
10 KiB
C
474 lines
10 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <hypervisor.h>
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/* Register offsets */
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#define IOAPIC_REGSEL_OFFSET 0
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#define IOAPIC_WINSWL_OFFSET 0x10
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#define IOAPIC_MAX_PIN 256
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/* IOAPIC Redirection Table (RTE) Entry structure */
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struct ioapic_rte {
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uint32_t lo_32;
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uint32_t hi_32;
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} ioapic_rte;
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struct gsi_table {
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uint8_t ioapic_id;
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uint8_t pin;
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void *addr;
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};
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static struct gsi_table gsi_table[NR_MAX_GSI];
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static uint32_t nr_gsi;
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static spinlock_t ioapic_lock;
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static struct ioapic_rte saved_rte[CONFIG_NR_IOAPICS][IOAPIC_MAX_PIN];
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/*
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* the irq to ioapic pin mapping should extract from ACPI MADT table
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* hardcoded here
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*/
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uint16_t legacy_irq_to_pin[NR_LEGACY_IRQ] = {
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2U, /* IRQ0*/
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1U, /* IRQ1*/
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0U, /* IRQ2 connected to Pin0 (ExtInt source of PIC) if existing */
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3U, /* IRQ3*/
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4U, /* IRQ4*/
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5U, /* IRQ5*/
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6U, /* IRQ6*/
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7U, /* IRQ7*/
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8U, /* IRQ8*/
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9U | IOAPIC_RTE_TRGRLVL, /* IRQ9*/
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10U, /* IRQ10*/
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11U, /* IRQ11*/
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12U, /* IRQ12*/
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13U, /* IRQ13*/
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14U, /* IRQ14*/
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15U, /* IRQ15*/
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};
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uint16_t pic_ioapic_pin_map[NR_LEGACY_PIN] = {
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2U, /* pin0*/
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1U, /* pin1*/
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0U, /* pin2*/
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3U, /* pin3*/
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4U, /* pin4*/
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5U, /* pin5*/
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6U, /* pin6*/
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7U, /* pin7*/
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8U, /* pin8*/
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9U, /* pin9*/
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10U, /* pin10*/
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11U, /* pin11*/
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12U, /* pin12*/
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13U, /* pin13*/
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14U, /* pin14*/
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15U, /* pin15*/
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};
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static void *map_ioapic(uint64_t ioapic_paddr)
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{
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/* At some point we may need to translate this paddr to a vaddr.
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* 1:1 mapping for now.
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*/
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return HPA2HVA(ioapic_paddr);
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}
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static inline uint32_t
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ioapic_read_reg32(const void *ioapic_base, const uint8_t offset)
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{
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uint32_t v;
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spinlock_rflags;
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spinlock_irqsave_obtain(&ioapic_lock);
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/* Write IOREGSEL */
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mmio_write_long(offset, (void *)ioapic_base);
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/* Read IOWIN */
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v = mmio_read_long((void *)ioapic_base + IOAPIC_WINSWL_OFFSET);
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spinlock_irqrestore_release(&ioapic_lock);
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return v;
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}
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static inline void
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ioapic_write_reg32(const void *ioapic_base,
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const uint8_t offset, const uint32_t value)
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{
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spinlock_rflags;
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spinlock_irqsave_obtain(&ioapic_lock);
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/* Write IOREGSEL */
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mmio_write_long(offset, (void *)ioapic_base);
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/* Write IOWIN */
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mmio_write_long(value, (void *)ioapic_base + IOAPIC_WINSWL_OFFSET);
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spinlock_irqrestore_release(&ioapic_lock);
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}
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static inline uint64_t
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get_ioapic_base(int apic_id)
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{
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uint64_t addr = -1UL;
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/* should extract next ioapic from ACPI MADT table */
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if (apic_id == 0)
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addr = DEFAULT_IO_APIC_BASE;
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else if (apic_id == 1)
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addr = 0xfec3f000;
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else if (apic_id == 2)
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addr = 0xfec7f000;
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else
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ASSERT(apic_id <= 2, "ACPI MADT table missing");
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return addr;
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}
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static inline void
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ioapic_get_rte_entry(void *ioapic_addr,
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int pin, struct ioapic_rte *rte)
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{
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rte->lo_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x10);
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rte->hi_32 = ioapic_read_reg32(ioapic_addr, pin*2 + 0x11);
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}
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static inline void
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ioapic_set_rte_entry(void *ioapic_addr,
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int pin, struct ioapic_rte *rte)
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{
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ioapic_write_reg32(ioapic_addr, pin*2 + 0x10, rte->lo_32);
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ioapic_write_reg32(ioapic_addr, pin*2 + 0x11, rte->hi_32);
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}
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static inline struct ioapic_rte
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create_rte_for_legacy_irq(uint32_t irq, uint32_t vr)
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{
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struct ioapic_rte rte = {0, 0};
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/* Legacy IRQ 0-15 setup, default masked
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* are actually defined in either MPTable or ACPI MADT table
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* before we have ACPI table parsing in HV we use common hardcode
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*/
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rte.lo_32 |= IOAPIC_RTE_INTMSET;
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rte.lo_32 |= (legacy_irq_to_pin[irq] & IOAPIC_RTE_TRGRLVL);
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rte.lo_32 |= DEFAULT_DEST_MODE;
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rte.lo_32 |= DEFAULT_DELIVERY_MODE;
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rte.lo_32 |= (IOAPIC_RTE_INTVEC & vr);
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/* FIXME: Fixed to active Low? */
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rte.lo_32 |= IOAPIC_RTE_INTALO;
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/* Dest field: legacy irq fixed to CPU0 */
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rte.hi_32 |= 1U << 24;
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return rte;
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}
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static inline struct ioapic_rte
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create_rte_for_gsi_irq(uint32_t irq, uint32_t vr)
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{
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struct ioapic_rte rte = {0, 0};
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if (irq < NR_LEGACY_IRQ)
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return create_rte_for_legacy_irq(irq, vr);
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/* irq default masked, level trig */
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rte.lo_32 |= IOAPIC_RTE_INTMSET;
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rte.lo_32 |= IOAPIC_RTE_TRGRLVL;
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rte.lo_32 |= DEFAULT_DEST_MODE;
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rte.lo_32 |= DEFAULT_DELIVERY_MODE;
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rte.lo_32 |= (IOAPIC_RTE_INTVEC & vr);
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/* FIXME: Fixed to active Low? */
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rte.lo_32 |= IOAPIC_RTE_INTALO;
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/* Dest field */
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rte.hi_32 |= ALL_CPUS_MASK << 24U;
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return rte;
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}
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static void ioapic_set_routing(uint32_t gsi, uint32_t vr)
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{
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void *addr;
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struct ioapic_rte rte;
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addr = gsi_table[gsi].addr;
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rte = create_rte_for_gsi_irq(gsi, vr);
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ioapic_set_rte_entry(addr, gsi_table[gsi].pin, &rte);
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if ((rte.lo_32 & IOAPIC_RTE_TRGRMOD) != 0U)
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update_irq_handler(gsi, handle_level_interrupt_common);
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else
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update_irq_handler(gsi, common_handler_edge);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%d rte:%x",
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gsi, gsi_table[gsi].pin,
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rte.lo_32);
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}
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void ioapic_get_rte(uint32_t irq, uint64_t *rte)
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{
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void *addr;
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struct ioapic_rte _rte;
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if (!irq_is_gsi(irq))
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return;
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addr = gsi_table[irq].addr;
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ioapic_get_rte_entry(addr, gsi_table[irq].pin, &_rte);
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*rte = _rte.hi_32;
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*rte = *rte << 32 | _rte.lo_32;
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}
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void ioapic_set_rte(uint32_t irq, uint64_t raw_rte)
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{
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void *addr;
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struct ioapic_rte rte;
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if (!irq_is_gsi(irq))
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return;
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addr = gsi_table[irq].addr;
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rte.lo_32 = raw_rte;
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rte.hi_32 = raw_rte >> 32;
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ioapic_set_rte_entry(addr, gsi_table[irq].pin, &rte);
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dev_dbg(ACRN_DBG_IRQ, "GSI: irq:%d pin:%d rte:%x",
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irq, gsi_table[irq].pin,
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rte.lo_32);
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}
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uint32_t irq_gsi_num(void)
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{
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return nr_gsi;
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}
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bool irq_is_gsi(uint32_t irq)
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{
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return irq < nr_gsi;
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}
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int irq_to_pin(uint32_t irq)
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{
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if (irq_is_gsi(irq))
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return gsi_table[irq].pin;
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else
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return -1;
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}
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uint32_t pin_to_irq(int pin)
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{
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uint32_t i;
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if (pin < 0)
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return IRQ_INVALID;
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for (i = 0; i < nr_gsi; i++) {
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if (gsi_table[i].pin == (uint8_t) pin)
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return i;
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}
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return IRQ_INVALID;
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}
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void
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irq_gsi_mask_unmask(uint32_t irq, bool mask)
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{
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void *addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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if (!irq_is_gsi(irq))
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return;
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ioapic_get_rte_entry(addr, pin, &rte);
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if (mask)
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rte.lo_32 |= IOAPIC_RTE_INTMSET;
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else
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rte.lo_32 &= ~IOAPIC_RTE_INTMASK;
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ioapic_set_rte_entry(addr, pin, &rte);
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dev_dbg(ACRN_DBG_PTIRQ, "update: irq:%d pin:%d rte:%x",
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irq, pin, rte.lo_32);
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}
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void setup_ioapic_irq(void)
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{
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int ioapic_id;
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uint32_t gsi;
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uint32_t vr;
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spinlock_init(&ioapic_lock);
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for (ioapic_id = 0, gsi = 0; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
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int pin;
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int max_pins;
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int version;
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void *addr;
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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version = ioapic_read_reg32(addr, IOAPIC_VER);
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max_pins = (version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT;
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dev_dbg(ACRN_DBG_IRQ, "IOAPIC version: %x", version);
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ASSERT(max_pins > NR_LEGACY_IRQ,
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"Legacy IRQ num > total GSI");
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for (pin = 0; pin < max_pins; pin++) {
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gsi_table[gsi].ioapic_id = ioapic_id;
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gsi_table[gsi].addr = addr;
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if (gsi < NR_LEGACY_IRQ)
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gsi_table[gsi].pin =
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legacy_irq_to_pin[gsi] & 0xffU;
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else
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gsi_table[gsi].pin = pin;
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/* pinned irq before use it */
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if (irq_mark_used(gsi) > NR_MAX_IRQS) {
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pr_err("failed to alloc IRQ[%d]", gsi);
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gsi++;
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continue;
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}
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/* assign vector for this GSI
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* for legacy irq, reserved vector and never free
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*/
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if (gsi < NR_LEGACY_IRQ) {
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vr = irq_desc_alloc_vector(gsi, false);
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if (vr > NR_MAX_VECTOR) {
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pr_err("failed to alloc VR");
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gsi++;
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continue;
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}
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} else
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vr = 0; /* not to allocate VR right now */
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ioapic_set_routing(gsi, vr);
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gsi++;
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}
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}
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/* system max gsi numbers */
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nr_gsi = gsi;
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ASSERT(nr_gsi < NR_MAX_GSI, "GSI table overflow");
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}
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void dump_ioapic(void)
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{
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uint32_t irq;
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for (irq = 0; irq < nr_gsi; irq++) {
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void *addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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ioapic_get_rte_entry(addr, pin, &rte);
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dev_dbg(ACRN_DBG_IRQ, "DUMP: irq:%d pin:%d rte:%x",
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irq, pin, rte.lo_32);
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}
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}
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void suspend_ioapic(void)
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{
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int ioapic_id, ioapic_pin;
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for (ioapic_id = 0; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
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int max_pins;
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int version;
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void *addr;
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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version = ioapic_read_reg32(addr, IOAPIC_VER);
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max_pins = (version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT;
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for (ioapic_pin = 0; ioapic_pin < max_pins; ioapic_pin++)
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ioapic_get_rte_entry(addr, ioapic_pin,
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&saved_rte[ioapic_id][ioapic_pin]);
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}
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}
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void resume_ioapic(void)
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{
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int ioapic_id, ioapic_pin;
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for (ioapic_id = 0; ioapic_id < CONFIG_NR_IOAPICS; ioapic_id++) {
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int max_pins;
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int version;
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void *addr;
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addr = map_ioapic(get_ioapic_base(ioapic_id));
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version = ioapic_read_reg32(addr, IOAPIC_VER);
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max_pins = (version & IOAPIC_MAX_RTE_MASK) >> MAX_RTE_SHIFT;
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for (ioapic_pin = 0; ioapic_pin < max_pins; ioapic_pin++)
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ioapic_set_rte_entry(addr, ioapic_pin,
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&saved_rte[ioapic_id][ioapic_pin]);
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}
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}
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#ifdef HV_DEBUG
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void get_rte_info(struct ioapic_rte *rte, bool *mask, bool *irr,
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bool *phys, int *delmode, bool *level, int *vector, uint32_t *dest)
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{
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*mask = ((rte->lo_32 & IOAPIC_RTE_INTMASK) == IOAPIC_RTE_INTMSET);
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*irr = ((rte->lo_32 & IOAPIC_RTE_REM_IRR) == IOAPIC_RTE_REM_IRR);
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*phys = ((rte->lo_32 & IOAPIC_RTE_DESTMOD) == IOAPIC_RTE_DESTPHY);
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*delmode = rte->lo_32 & IOAPIC_RTE_DELMOD;
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*level = ((rte->lo_32 & IOAPIC_RTE_TRGRLVL) != 0U) ? true : false;
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*vector = rte->lo_32 & IOAPIC_RTE_INTVEC;
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*dest = rte->hi_32 >> APIC_ID_SHIFT;
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}
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int get_ioapic_info(char *str, int str_max_len)
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{
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uint32_t irq, len, size = str_max_len;
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len = snprintf(str, size,
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"\r\nIRQ\tPIN\tRTE.HI32\tRTE.LO32\tVEC\tDST\tDM\tTM\tDELM\tIRR\tMASK");
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size -= len;
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str += len;
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for (irq = 0; irq < nr_gsi; irq++) {
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void *addr = gsi_table[irq].addr;
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int pin = gsi_table[irq].pin;
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struct ioapic_rte rte;
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bool irr, phys, level, mask;
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int delmode, vector;
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uint32_t dest;
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ioapic_get_rte_entry(addr, pin, &rte);
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get_rte_info(&rte, &mask, &irr, &phys, &delmode, &level,
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&vector, &dest);
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len = snprintf(str, size, "\r\n%03d\t%03d\t0x%08X\t0x%08X\t",
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irq, pin, rte.hi_32, rte.lo_32);
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size -= len;
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str += len;
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len = snprintf(str, size, "0x%02X\t0x%02X\t%s\t%s\t%d\t%d\t%d",
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vector, dest, phys ? "phys" : "logic",
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level ? "level" : "edge", delmode >> 8, irr, mask);
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size -= len;
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str += len;
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if (size < 2) {
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pr_err("\r\nsmall buffer for ioapic dump");
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return -1;
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}
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}
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snprintf(str, size, "\r\n");
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return 0;
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}
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#endif /* HV_DEBUG */
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