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286c383b53
add dummy headrer file for early compile, should be replaced totally later. Tracked-On: #8801 Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Wang, Yu1 <yu1.wang@intel.com> Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
58 lines
1.2 KiB
C
58 lines
1.2 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef RISCV_CPU_H
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#define RISCV_CPU_H
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#include <types.h>
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#include <lib/util.h>
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/* CPU states defined */
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enum pcpu_boot_state {
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PCPU_STATE_RESET = 0U,
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PCPU_STATE_INITIALIZING,
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PCPU_STATE_RUNNING,
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PCPU_STATE_HALTED,
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PCPU_STATE_DEAD,
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};
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static inline void wait_sync_change(__unused volatile const uint64_t *sync, __unused uint64_t wake_sync)
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{
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/**
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* Dummy implementation.
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* Official implementations are to be provided in the platform initialization patchset (by Hang).
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*/
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}
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static inline bool is_pcpu_active(__unused uint16_t pcpu_id)
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{
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/**
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* Dummy implementation.
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* Official implementations are to be provided in the platform initialization patchset (by Hang).
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*/
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return true;
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}
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static inline uint16_t get_pcpu_id(void)
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{
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/**
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* Dummy implementation.
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* Official implementations are to be provided in the platform initialization patchset (by Hang).
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*/
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return 0U;
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}
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/* Write CSR */
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#define cpu_csr_write(reg, csr_val) \
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({ \
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uint64_t val = (uint64_t)csr_val; \
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asm volatile (" csrw " STRINGIFY(reg) ", %0 \n\t" \
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:: "r"(val): "memory"); \
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})
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#endif /* RISCV_CPU_H */
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