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Add cfg_header_read_cfg and cfg_header_write_cfg to handle the 1st 64B CFG Space header PCI configuration space. Only Command and Status Registers are pass through; Only Command and Status Registers and Base Address Registers are writable. In order to implement this, we add two type bit mask for per 4B register: pass through mask and read-only mask. When pass through bit mask is set, this means this bit of this 4B register is pass through, otherwise, it is virtualized; When read-only mask is set, this means this bit of this 4B register is read-only, otherwise, it's writable. We should write it to physical CFG space or virtual CFG space base on whether the pass through bit mask is set or not. Tracked-On: #4371 Signed-off-by: Li Fei1 <fei1.li@intel.com>
ACRN Hypervisor ############### The open source `Project ACRN`_ defines a device hypervisor reference stack and an architecture for running multiple software subsystems, managed securely, on a consolidated system by means of a virtual machine manager. It also defines a reference framework implementation for virtual device emulation, called the "ACRN Device Model". The ACRN Hypervisor is a Type 1 reference hypervisor stack, running directly on the bare-metal hardware, and is suitable for a variety of IoT and embedded device solutions. The ACRN hypervisor addresses the gap that currently exists between datacenter hypervisors, and hard partitioning hypervisors. The ACRN hypervisor architecture partitions the system into different functional domains, with carefully selected guest OS sharing optimizations for IoT and embedded devices. You can find out more about Project ACRN on the `Project ACRN documentation`_ website. .. _`Project ACRN`: https://projectacrn.org .. _`ACRN Hypervisor`: https://github.com/projectacrn/acrn-hypervisor .. _`Project ACRN documentation`: https://projectacrn.github.io/