Files
acrn-hypervisor/hypervisor/arch/riscv/boot/cpu_entry.S
Jian Jun Chen 1dee977429 hv: risc-v: add relocation support
This patch implements relocation support for ACRN RISC-V to enable
position-independent execution. The hypervisor can now be loaded at any
physical address and will automatically relocate itself at runtime. Key
changes:
- Add relocate() function to process R_RISCV_RELATIVE relocations in
  .rela sections during early boot
- Implement arch_get_hv_image_delta() to calculate the load address offset
  from the configured base address
- Add relocation processing in cpu_entry.S before jumping to C code
- Update linker script to include .rela sections for relocation data
- Define R_RISCV_RELATIVE relocation type and linker symbol definitions

Tracked-On: #8825
Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-10-22 10:15:01 +08:00

77 lines
1.3 KiB
ArmAsm

/*
* Copyright (C) 2025 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Authors:
* Haicheng Li <haicheng.li@intel.com>
*/
.section .text.entry, "ax", %progbits
/*
* main entry point
* - a0 = hart ID
* - a1 = dtb address
*/
.globl _start
_start:
/* Mask all interrupts */
csrw sie, zero
/* Disable FPU bit[14:13] */
li t0, 0x00006000
csrc sstatus, t0
/* Set trap vector to spin forever for debug */
lla a3, _start_hang
csrw stvec, a3
/* Clear BSS */
lla t3, _bss_start
lla t4, _bss_end
_clear_bss:
sd zero, (t3)
add t3, t3, __SIZEOF_POINTER__
bltu t3, t4, _clear_bss
/* Setup cpu0 boot stack (full descending) */
lla sp, _boot_stack_end
#ifdef CONFIG_RELOC
mv s1, a0
lla a0, _DYNAMIC
/* Fix up the .rela sections */
call relocate
mv a0, s1
#endif /* CONFIG_RELOC */
/* a0 = hart_id, a1 = dtb_address */
tail init_primary_pcpu
.align 2
.global _start_secondary_sbi
_start_secondary_sbi:
/* Mask all interrupts */
csrw sie, zero
/* Disable FPU bit[14:13] */
li t0, 0x00006000
csrc sstatus, t0
/* Set trap vector to spin forever for debug */
lla a3, _start_hang
csrw stvec, a3
/* a0 contains the hartid & a1 contains stack physical addr */
mv sp, a1
tail init_secondary_pcpu
.align 2
_start_hang:
wfi
j _start_hang