Yin Fengwei 4579e57e7b hv: add gva check for the case gva is from instruction decode ... For the instructions other than MOVS, one operand is register and another one is memory which trigger EPT voilation. In this case, there is one possibility that EPT voilation happens before guest fault: the fault is triggered by related guest PTE access bit voilation (like write to a gva with R/W bit cleared in PTE). So we do this kind of check and inject exception to guest accordingly during instruction decoding phase. Signed-off-by: Yin Fengwei <fengwei.yin@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>		2018-08-23 11:13:48 +08:00
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x86	hv: add gva check for the case gva is from instruction decode	2018-08-23 11:13:48 +08:00