Files
acrn-hypervisor/hypervisor/include/arch/riscv/asm/mmu.h
hangliu1 47ed22bef8 hv: riscv: add check for other memory mode
Check whether SV48 is supported, panic if not.

Tracked-On: #8831
Signed-off-by: hangliu1 <hang1.liu@intel.com>
Reviewed-by: Liu, Yifan1 <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-10-21 14:14:55 +08:00

25 lines
389 B
C

/*
* Copyright (C) 2023-2025 Intel Corporation.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef RISCV_MMU_H
#define RISCV_MMU_H
#include <types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
static inline void set_satp(uint64_t satp)
{
asm volatile (
"csrw satp, %0\n\t" \
"sfence.vma"
:: "r"(satp)
: "memory"
);
}
void init_paging(void);
#endif /* RISCV_MMU_H */