Binbin Wu 4ae350a091 hv: vmcs: pass-through instruction INVPCID to VM ... According to SDM Vol.3 Section 25.3, behavior of the INVPCID instruction is determined first by the setting of the “enable INVPCID” VM-execution control: - If the “enable INVPCID” VM-execution control is 0, INVPCID causes an invalid-opcode exception (#UD). - If the “enable INVPCID” VM-execution control is 1, treatment is based on the setting of the “INVLPG exiting” VM-execution control: * If the “INVLPG exiting” VM-execution control is 0, INVPCID operates normally. * If the “INVLPG exiting” VM-execution control is 1, INVPCID causes a VM exit. In current implementation, hypervisor doesn't set “INVLPG exiting” VM-execution control, this patch sets “enable INVPCID” VM-execution control to 1 when the instruction is supported by physical cpu. If INVPCID is supported by physical cpu, INVPCID will not cause VM exit in VM. If INVPCID is not supported by physical cpu, INVPCID causes an #UD in VM. When INVPCID is passed-through to VM, According to SDM Vol.3 28.3.3.1, INVPCID instruction invalidates linear mappings and combined mappings. They are required to do so only for the current VPID. HV assigned a unique vpid for each vCPU, if guest uses wrong PCID, it would not affect other vCPUs. Tracked-On: #4296 Signed-off-by: Binbin Wu <binbin.wu@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2020-01-02 10:47:34 +08:00
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x86	hv: vmcs: pass-through instruction INVPCID to VM	2020-01-02 10:47:34 +08:00