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https://github.com/projectacrn/acrn-hypervisor.git
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f7c4d2b5c4
Use nr_bars instead of PCI_BAR_COUNT to check bar access offset. As while normal pci device has max 6 bars, pci bridge only has 2 bars, so for pci normal pci device, pci cfg offsets 0x10-0x24 are for bar access, but for pci bridge, only 0x10-0x14 are for bar access (0x18-0x24 are for other accesses). Rename function: pci_bar_access --> is_bar_offset Tracked-On: #3241 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
139 lines
4.6 KiB
C
139 lines
4.6 KiB
C
/*-
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* Copyright (c) 2011 NetApp, Inc.
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*_
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* Emulate a PCI Host bridge:
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* Intel Corporation Celeron N3350/Pentium N4200/Atom E3900
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* Series Host Bridge (rev 0b)
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*/
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#include <vm.h>
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#include <pci.h>
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#include <errno.h>
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#include "vpci_priv.h"
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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* @pre vdev->vpci->vm != NULL
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*/
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void init_vhostbridge(struct pci_vdev *vdev)
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{
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if (is_hostbridge(vdev) && is_prelaunched_vm(vdev->vpci->vm)) {
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/* PCI config space */
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pci_vdev_write_cfg_u16(vdev, PCIR_VENDOR, (uint16_t)0x8086U);
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pci_vdev_write_cfg_u16(vdev, PCIR_DEVICE, (uint16_t)0x5af0U);
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pci_vdev_write_cfg_u8(vdev, PCIR_REVID, (uint8_t)0xbU);
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pci_vdev_write_cfg_u8(vdev, PCIR_HDRTYPE, (uint8_t)PCIM_HDRTYPE_NORMAL
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| PCIM_MFDEV);
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pci_vdev_write_cfg_u8(vdev, PCIR_CLASS, (uint8_t)PCIC_BRIDGE);
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pci_vdev_write_cfg_u8(vdev, PCIR_SUBCLASS, (uint8_t)PCIS_BRIDGE_HOST);
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pci_vdev_write_cfg_u8(vdev, 0x34U, (uint8_t)0xe0U);
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pci_vdev_write_cfg_u8(vdev, 0x3cU, (uint8_t)0xe0U);
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pci_vdev_write_cfg_u8(vdev, 0x48U, (uint8_t)0x1U);
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pci_vdev_write_cfg_u8(vdev, 0x4aU, (uint8_t)0xd1U);
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pci_vdev_write_cfg_u8(vdev, 0x4bU, (uint8_t)0xfeU);
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pci_vdev_write_cfg_u8(vdev, 0x50U, (uint8_t)0xc1U);
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pci_vdev_write_cfg_u8(vdev, 0x51U, (uint8_t)0x2U);
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pci_vdev_write_cfg_u8(vdev, 0x54U, (uint8_t)0x33U);
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pci_vdev_write_cfg_u8(vdev, 0x58U, (uint8_t)0x7U);
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pci_vdev_write_cfg_u8(vdev, 0x5aU, (uint8_t)0xf0U);
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pci_vdev_write_cfg_u8(vdev, 0x5bU, (uint8_t)0x7fU);
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pci_vdev_write_cfg_u8(vdev, 0x60U, (uint8_t)0x1U);
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pci_vdev_write_cfg_u8(vdev, 0x63U, (uint8_t)0xe0U);
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pci_vdev_write_cfg_u8(vdev, 0xabU, (uint8_t)0x80U);
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pci_vdev_write_cfg_u8(vdev, 0xacU, (uint8_t)0x2U);
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pci_vdev_write_cfg_u8(vdev, 0xb0U, (uint8_t)0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xb3U, (uint8_t)0x7cU);
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pci_vdev_write_cfg_u8(vdev, 0xb4U, (uint8_t)0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xb6U, (uint8_t)0x80U);
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pci_vdev_write_cfg_u8(vdev, 0xb7U, (uint8_t)0x7bU);
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pci_vdev_write_cfg_u8(vdev, 0xb8U, (uint8_t)0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xbbU, (uint8_t)0x7bU);
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pci_vdev_write_cfg_u8(vdev, 0xbcU, (uint8_t)0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xbfU, (uint8_t)0x80U);
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pci_vdev_write_cfg_u8(vdev, 0xe0U, (uint8_t)0x9U);
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pci_vdev_write_cfg_u8(vdev, 0xe2U, (uint8_t)0xcU);
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pci_vdev_write_cfg_u8(vdev, 0xe3U, (uint8_t)0x1U);
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pci_vdev_write_cfg_u8(vdev, 0xf5U, (uint8_t)0xfU);
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pci_vdev_write_cfg_u8(vdev, 0xf6U, (uint8_t)0x1cU);
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pci_vdev_write_cfg_u8(vdev, 0xf7U, (uint8_t)0x1U);
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}
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}
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void deinit_vhostbridge(__unused const struct pci_vdev *vdev)
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{
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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* @pre vdev->vpci->vm != NULL
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*/
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int32_t vhostbridge_read_cfg(const struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t *val)
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{
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int32_t ret = -ENODEV;
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if (is_hostbridge(vdev) && is_prelaunched_vm(vdev->vpci->vm)) {
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*val = pci_vdev_read_cfg(vdev, offset, bytes);
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ret = 0;
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}
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return ret;
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}
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/**
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* @pre vdev != NULL
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* @pre vdev->vpci != NULL
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* @pre vdev->vpci->vm != NULL
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*/
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int32_t vhostbridge_write_cfg(struct pci_vdev *vdev, uint32_t offset,
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uint32_t bytes, uint32_t val)
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{
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int32_t ret = -ENODEV;
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if (is_hostbridge(vdev) && is_prelaunched_vm(vdev->vpci->vm)) {
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if (!is_bar_offset(PCI_BAR_COUNT, offset)) {
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pci_vdev_write_cfg(vdev, offset, bytes, val);
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}
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ret = 0;
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}
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return ret;
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}
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