mirror of
https://github.com/projectacrn/acrn-hypervisor.git
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4dc39fdb8e
There are some integer type conversions reported by static analysis tool for vcpu id, number of created vcpus, and vpid, to reduce these type conversions, redesign vcpu id, number of created vcpus, and vpid type as uint16_t as per their usage, related 16-bit atomic operations shall be added in HV. MISRA C requires that all unsigned constants should have the suffix 'U' (e.g. 0xffU), but the assembler may not accept such C-style constants. Add 16-bit atomic add/dec/store operations; Update temporary variables type and parameters type of related caller; Update vpid type as uint16_t; Replace Macro with constant value for CPU_PAGE_SIZE. Note: According to SDM A.10, there are some bits defined in the IA32_VMX_EPT_VPID_CAP MSR to support the INVVPID instruction, these bits don't mean actual VPID, so the vpid field in the data struct vmx_capability doesn't be updated. V1--V2: update comments for assembly code as per coding style; Signed-off-by: Xiangyang Wu <xiangyang.wu@intel.com>
189 lines
5.6 KiB
C
189 lines
5.6 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* Copyright (c) 2018 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef ATOMIC_H
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#define ATOMIC_H
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#define BUS_LOCK "lock ; "
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#define build_atomic_load(name, size, type, ptr) \
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static inline type name(const volatile type *ptr) \
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{ \
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type ret; \
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asm volatile("mov" size " %1,%0" \
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: "=r" (ret) \
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: "m" (*ptr) \
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: "cc", "memory"); \
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return ret; \
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}
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build_atomic_load(atomic_load, "l", int, p)
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build_atomic_load(atomic_load64, "q", long, p)
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#define build_atomic_store(name, size, type, ptr, v) \
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static inline void name(volatile type *ptr, type v) \
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{ \
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asm volatile("mov" size " %1,%0" \
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: "=m" (*ptr) \
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: "r" (v) \
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: "cc", "memory"); \
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}
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build_atomic_store(atomic_store16, "w", uint16_t, p, v)
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build_atomic_store(atomic_store, "l", int, p, v)
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build_atomic_store(atomic_store64, "q", long, p, v)
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#define build_atomic_inc(name, size, type, ptr) \
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static inline void name(type *ptr) \
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{ \
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asm volatile(BUS_LOCK "inc" size " %0" \
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: "=m" (*ptr) \
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: "m" (*ptr)); \
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}
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build_atomic_inc(atomic_inc, "l", int, p)
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build_atomic_inc(atomic_inc64, "q", long, p)
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#define build_atomic_dec(name, size, type, ptr) \
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static inline void name(type *ptr) \
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{ \
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asm volatile(BUS_LOCK "dec" size " %0" \
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: "=m" (*ptr) \
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: "m" (*ptr)); \
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}
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build_atomic_dec(atomic_dec16, "w", uint16_t, p)
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build_atomic_dec(atomic_dec, "l", int, p)
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build_atomic_dec(atomic_dec64, "q", long, p)
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/*
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* #define atomic_set_int(P, V) (*(unsigned int *)(P) |= (V))
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*/
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static inline void atomic_set_int(unsigned int *p, unsigned int v)
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{
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__asm __volatile(BUS_LOCK "orl %1,%0"
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: "+m" (*p)
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: "r" (v)
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: "cc", "memory");
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}
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/*
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* #define atomic_clear_int(P, V) (*(unsigned int *)(P) &= ~(V))
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*/
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static inline void atomic_clear_int(unsigned int *p, unsigned int v)
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{
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__asm __volatile(BUS_LOCK "andl %1,%0"
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: "+m" (*p)
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: "r" (~v)
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: "cc", "memory");
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}
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/*
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* #define atomic_set_long(P, V) (*(unsigned long *)(P) |= (V))
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*/
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static inline void atomic_set_long(unsigned long *p, unsigned long v)
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{
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__asm __volatile(BUS_LOCK "orq %1,%0"
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: "+m" (*p)
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: "r" (v)
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: "cc", "memory");
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}
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/*
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* #define atomic_clear_long(P, V) (*(u_long *)(P) &= ~(V))
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*/
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static inline void atomic_clear_long(unsigned long *p, unsigned long v)
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{
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__asm __volatile(BUS_LOCK "andq %1,%0"
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: "+m" (*p)
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: "r" (~v)
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: "cc", "memory");
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}
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#define build_atomic_swap(name, size, type, ptr, v) \
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static inline type name(type *ptr, type v) \
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{ \
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asm volatile(BUS_LOCK "xchg" size " %1,%0" \
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: "+m" (*ptr), "+r" (v) \
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: \
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: "cc", "memory"); \
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return v; \
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}
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build_atomic_swap(atomic_swap, "l", int, p, v)
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build_atomic_swap(atomic_swap64, "q", long, p, v)
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/*
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* #define atomic_readandclear(P) \
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* (return (*(int *)(P)); *(int *)(P) = 0;)
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*/
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#define atomic_readandclear(p) atomic_swap(p, 0)
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/*
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* #define atomic_readandclear64(P) \
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* (return (*(long *)(P)); *(long *)(P) = 0;)
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*/
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#define atomic_readandclear64(p) atomic_swap64(p, 0)
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#define build_atomic_cmpxchg(name, size, type, ptr, old, new) \
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static inline type name(volatile type *ptr, \
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type old, type new) \
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{ \
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type ret; \
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asm volatile(BUS_LOCK "cmpxchg" size " %2,%1" \
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: "=a" (ret), "+m" (*p) \
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: "r" (new), "0" (old) \
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: "memory"); \
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return ret; \
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}
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build_atomic_cmpxchg(atomic_cmpxchg, "l", int, p, old, new)
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build_atomic_cmpxchg(atomic_cmpxchg64, "q", long, p, old, new)
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#define build_atomic_xadd(name, size, type, ptr, v) \
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static inline type name(type *ptr, type v) \
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{ \
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asm volatile(BUS_LOCK "xadd" size " %0,%1" \
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: "+r" (v), "+m" (*p) \
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: \
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: "cc", "memory"); \
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return v; \
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}
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build_atomic_xadd(atomic_xadd16, "w", uint16_t, p, v)
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build_atomic_xadd(atomic_xadd, "l", int, p, v)
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build_atomic_xadd(atomic_xadd64, "q", long, p, v)
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#define atomic_add_return(p, v) ( atomic_xadd(p, v) + v )
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#define atomic_sub_return(p, v) ( atomic_xadd(p, -v) - v )
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#define atomic_inc_return(v) atomic_add_return((v), 1)
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#define atomic_dec_return(v) atomic_sub_return((v), 1)
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#define atomic_add64_return(p, v) ( atomic_xadd64(p, v) + v )
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#define atomic_sub64_return(p, v) ( atomic_xadd64(p, -v) - v )
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#define atomic_inc64_return(v) atomic_add64_return((v), 1)
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#define atomic_dec64_return(v) atomic_sub64_return((v), 1)
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#endif /* ATOMIC_H*/
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