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https://github.com/projectacrn/acrn-hypervisor.git
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b88fb1fc46
Add stack protector implementation for RISC-V architecture using a global __stack_chk_guard variable. This differs from x86 which uses per-CPU stack canaries. Tracked-On: #8834 Signed-off-by: Jian Jun Chen <jian.jun.chen@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
135 lines
2.8 KiB
C
135 lines
2.8 KiB
C
/*
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* Copyright (C) 2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#include <types.h>
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#include <cpu.h>
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#include <per_cpu.h>
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#include <logmsg.h>
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#include <mmu.h>
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#include <timer.h>
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#include <console.h>
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#include <shell.h>
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#include <uart16550.h>
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#ifdef STACK_PROTECTOR
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#include <asm/security.h>
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#endif
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static void init_pcpu_comm_post(void);
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/* Push sp magic to top of stack for call trace */
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#define SWITCH_TO(sp, to) \
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{ \
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asm volatile ( \
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"mv sp, %0\n" /* Set stack pointer */ \
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"addi sp, sp, -8\n" /* Make room for magic value */ \
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"sd %1, 0(sp)\n" /* Store magic value */ \
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"jalr %2\n" /* Jump to function pointer */ \
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: \
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: "r"(sp), "r"(SP_BOTTOM_MAGIC), "r"(to) \
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); \
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}
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static void init_debug_pre(void)
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{
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console_init();
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}
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static void init_debug_post(uint16_t pcpu_id)
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{
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if (pcpu_id == BSP_CPU_ID) {
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/* Initialize the shell */
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shell_init();
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}
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if (pcpu_id == VUART_TIMER_CPU) {
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console_setup_timer();
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}
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}
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/* C entry point for boot CPU */
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void init_primary_pcpu(uint64_t hart_id, uint64_t fdt_paddr)
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{
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uint16_t pcpu_id = BSP_CPU_ID;
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uint64_t pcpu_sp;
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(void)fdt_paddr;
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init_percpu_hart_id(hart_id);
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set_pcpu_active(pcpu_id);
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#ifdef STACK_PROTECTOR
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init_stack_canary();
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#endif
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/*
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* Set state for this CPU to initializing, the current pcpu_id
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* is set to a per-cpu register tp from now on.
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*/
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pcpu_set_current_state(pcpu_id, PCPU_STATE_INITIALIZING);
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init_debug_pre();
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init_paging();
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/*
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* Need update uart_base_address here for vaddr2paddr mapping may changed
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* WARNNING: DO NOT CALL PRINTF BETWEEN ENABLE PAGING IN init_paging AND HERE!
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*/
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uart16550_init(false);
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if (!start_pcpus(AP_MASK)) {
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panic("Failed to start all secondary cores!");
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}
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/* Switch to run-time stack */
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pcpu_sp = (uint64_t)(&get_cpu_var(stack)[CONFIG_STACK_SIZE - 1]);
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pcpu_sp &= ~(CPU_STACK_ALIGN - 1UL);
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SWITCH_TO(pcpu_sp, init_pcpu_comm_post);
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}
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/* C entry point for AP */
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void init_secondary_pcpu(uint64_t hart_id)
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{
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uint16_t pcpu_id;
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pcpu_id = get_pcpu_id_from_hart_id(hart_id);
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if (pcpu_id >= MAX_PCPU_NUM) {
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panic("Invalid pCPU ID!");
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}
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set_pcpu_active(pcpu_id);
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enable_paging();
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/*
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* Set state for this CPU to initializing, the current pcpu_id
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* is set to a per-cpu register tp from now on.
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*/
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pcpu_set_current_state(pcpu_id, PCPU_STATE_INITIALIZING);
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/* This function shall never return */
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init_pcpu_comm_post();
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}
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static void init_pcpu_comm_post(void)
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{
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uint16_t pcpu_id;
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pcpu_id = get_pcpu_id();
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if (pcpu_id == BSP_CPU_ID) {
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/* Print Hypervisor Banner */
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print_hv_banner();
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}
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init_interrupt(pcpu_id);
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timer_init();
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init_sched(pcpu_id);
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init_debug_post(pcpu_id);
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run_idle_thread();
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}
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