Zide Chen 5555a2f85d hv: fix bug in sizing MSI-X Table Base Address Register ... To sizing a 64-bit BAR, need to form the two 32-bit registers as a 64-bit words, before doing the calculation: inverting all bits and incrementing by 1. Tracked-On: #1568 Signed-off-by: dongshen <dongsheng.x.zhang@intel.com> Signed-off-by: Zide Chen <zide.chen@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>		2018-11-01 21:22:10 +08:00
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hw	hv: Don't check multi-function flag in PCI enumeration	2018-11-01 21:22:10 +08:00
vpci	hv: fix bug in sizing MSI-X Table Base Address Register	2018-11-01 21:22:10 +08:00
vioapic.c	hv: rework the MMIO handler callback hv_mem_io_handler_t arguments	2018-10-29 14:29:37 +08:00
vpic.c	hv: fix integer violations	2018-10-31 15:01:57 +08:00
vrtc.c	hv: merge hv_lib.h and hypervisor.h	2018-09-27 15:55:41 +08:00