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5803232d83aee2dc18c909ba08abc19fd0f5b7f7
acrn-hypervisor/hypervisor/include/arch/riscv/asm
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Jiaqing Zhao 5803232d83 hv: enable acrnlog in release builds 
Enable acrnlog (memory logging) in release builds, default log level
is still controlled by DEBUG_OPTIONS/MEM_LOGLEVEL in scenario file.

Tracked-On: #8805
Signed-off-by: Jiaqing Zhao <jiaqing.zhao@linux.intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>
2025-09-25 16:30:26 +08:00
..
guest
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00
lib
hv: multi-arch add RISC-V bits library implementation
2025-09-22 10:52:06 +08:00
cpu.h
hv: enable acrnlog in release builds
2025-09-25 16:30:26 +08:00
init.h
hv: risc-v: add C entry function of BSP and APs
2025-09-15 13:12:21 +08:00
irq.h
…
notify.h
hv: smpcall: riscv: implement SMP call handlers
2025-09-09 16:37:04 +08:00
page.h
enable common code compile
2025-09-19 15:04:55 +08:00
per_cpu.h
hv: riscv: add get/set_pcpu_id and start_pcpus implementation
2025-09-23 11:30:38 +08:00
pgtable.h
[FIXME] hv: riscv: add build dependencies temporarily
2025-09-23 11:30:38 +08:00
qemu.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
sbi.h
hv: riscv: add SBI HSM HART_START interface
2025-09-23 11:30:38 +08:00
security.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00
timer.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
vm_config.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00