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Follow multi-arch design, implement the mandatory arch spinlock functions declared in common spinlock.h for risc-v support. Tracked-On: #8803 Signed-off-by: Haicheng Li <haicheng.li@linux.intel.com> Signed-off-by: Haoyu Tang <haoyu.tang@intel.com> Reviewed-by: Yifan Liu <yifan1.liu@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
70 lines
1.6 KiB
C
70 lines
1.6 KiB
C
/*
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* Copyright (C) 2023-2025 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Authors:
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* Haicheng Li <haicheng.li@intel.com>
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*/
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#ifndef RISCV_LIB_SPINLOCK_H
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#define RISCV_LIB_SPINLOCK_H
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#ifndef ASSEMBLER
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/** The architecture dependent spinlock type. */
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typedef struct _arch_spinlock {
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uint64_t head;
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uint64_t tail;
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} arch_spinlock_t;
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static inline void arch_spinlock_obtain(arch_spinlock_t *lock)
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{
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asm volatile (" li t0, 0x1\n\t"
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" amoadd.d.aqrl t1, t0, (%[head])\n\t"
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"2: ld t0, (%[tail])\n\t"
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" beq t1, t0, 1f\n\t"
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" j 2b\n\t"
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"1:\n"
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:
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:
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[head] "r"(&lock->head),
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[tail] "r"(&lock->tail)
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: "cc", "memory", "t0", "t1");
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}
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static inline void arch_spinlock_release(arch_spinlock_t *lock)
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{
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asm volatile (" li t0, 0x1\n\t"
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" amoadd.d.aqrl t1, t0, (%[tail])\n"
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:
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: [tail] "r" (&lock->tail)
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: "cc", "memory", "t0", "t1");
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}
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#else /* ASSEMBLER */
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/** The offset of the head element. */
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#define SPINLOCK_HEAD_OFFSET 0
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/** The offset of the tail element. */
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#define SPINLOCK_TAIL_OFFSET 8
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.macro arch_spinlock_obtain lock_arg
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li t0, 0x1
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la t2, \lock_arg
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addi t3, t2, SPINLOCK_HEAD_OFFSET
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amoadd.d.aqrl t1, t0, (t3)
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2: ld t0, SPINLOCK_TAIL_OFFSET(t2)
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beq t1, t0, 1f
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j 2b
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1 :
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.endm
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#define arch_spinlock_obtain(x) arch_spinlock_obtain lock_arg = (x)
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.macro arch_spinlock_release lock_arg
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li t0, 0x1
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la t2, \lock_arg
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addi t3, t2, SPINLOCK_TAIL_OFFSET
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amoadd.d.aqrl t1, t0, (t3)
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.endm
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#define arch_spinlock_release(x) arch_spinlock_release lock_arg = (x)
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#endif /* ASSEMBLER */
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#endif /* RISCV_LIB_SPINLOCK_H */
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