Haiwei Li 59a8cc4c28 hv: cpuid: make leaf 0x4 per-cpu in hybrid architecture ...

Leaf 0x4 returns deterministic cache parameters for each level. In
hybrid architecture, P-cores and E-cores have different cache
information.

Add leaf 0x4 to per-cpu list in hybrid architecture and handle specific
cpuid access.

Tracked-On: #8608
Signed-off-by: Haiwei Li <haiwei.li@intel.com>

2024-05-28 11:02:56 +08:00

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boot

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configs

HV: emulate dummy multi-function dev in Service VM

2023-09-11 16:13:16 +08:00

guest

hv: cpuid: make leaf 0x4 per-cpu in hybrid architecture

2024-05-28 11:02:56 +08:00

lib

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seed

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cpu_caps.c

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cpu_state_tbl.c

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cpu.c

hv: enable thermal lvt interrupt

2024-05-16 09:40:32 +08:00

e820.c

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exception.c

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gdt.c

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hw_thermal.c

hv: enable thermal lvt interrupt

2024-05-16 09:40:32 +08:00

idt.S

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init.c

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ioapic.c

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irq.c

hv: enable thermal lvt interrupt

2024-05-16 09:40:32 +08:00

lapic.c

hypervisor: Fix spelling and grammar mistakes.

2023-10-23 16:45:28 +08:00

mmu.c

hv: mmu: intiialize ppt_page_pool.bitmap in allocate_ppt_pages()

2024-03-25 09:57:08 +08:00

nmi.c

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notify.c

hypervisor: Fix spelling and grammar mistakes.

2023-10-24 11:10:47 +08:00

page.c

hypervisor: Fix spelling and grammar mistakes.

2023-10-24 11:10:47 +08:00

pagetable.c

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platform_caps.c

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pm.c

hypervisor: Fix spelling and grammar mistakes.

2023-10-24 11:10:47 +08:00

rdt.c

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rtcm.c

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sched.S

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security.c

hv: refine set_fs_base() function

2024-04-23 11:00:43 +08:00

sgx.c

hv: sgx: refactor partition_epc()

2023-06-06 15:22:19 +08:00

trampoline.c

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tsc_deadline_timer.c

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tsc.c

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vmx.c

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vtd.c

doc: Fix spelling and typo mistakes.

2023-09-05 09:34:21 +08:00

wakeup.S

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