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https://github.com/projectacrn/acrn-hypervisor.git
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58b42baa74
There are many naming violations detected by static analysis tool. Data structure type name is the same as variable name. According to naming convention rules, If the data structure type is used by multi modules and its name meaning is simplistic (such as vcpu, vm), its name needs prefix "acrn_". Rename struct vpic as struct acrn_vpic. Replace regular expression:s/struct vpic\([ ),;\t\*]\+\)/struct acrn_vpic\1 Signed-off-by: Xiangyang Wu <xiangyang.wu@linux.intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
110 lines
4.1 KiB
C
110 lines
4.1 KiB
C
/*-
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* Copyright (c) 2014 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
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* Copyright (c) 2017 Intel Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _VPIC_H_
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#define _VPIC_H_
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#define ICU_IMR_OFFSET 1U
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/* Initialization control word 1. Written to even address. */
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#define ICW1_IC4 0x01U /* ICW4 present */
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#define ICW1_SNGL 0x02U /* 1 = single, 0 = cascaded */
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#define ICW1_ADI 0x04U /* 1 = 4, 0 = 8 byte vectors */
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#define ICW1_LTIM 0x08U /* 1 = level trigger, 0 = edge */
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#define ICW1_RESET 0x10U /* must be 1 */
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/* 0x20 - 0x80 - in 8080/8085 mode only */
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/* Initialization control word 2. Written to the odd address. */
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/* No definitions, it is the base vector of the IDT for 8086 mode */
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/* Initialization control word 3. Written to the odd address. */
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/* For a master PIC, bitfield indicating a slave 8259 on given input */
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/* For slave, lower 3 bits are the slave's ID binary id on master */
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/* Initialization control word 4. Written to the odd address. */
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#define ICW4_8086 0x01U /* 1 = 8086, 0 = 8080 */
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#define ICW4_AEOI 0x02U /* 1 = Auto EOI */
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#define ICW4_MS 0x04U /* 1 = buffered master, 0 = slave */
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#define ICW4_BUF 0x08U /* 1 = enable buffer mode */
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#define ICW4_SFNM 0x10U /* 1 = special fully nested mode */
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/* Operation control words. Written after initialization. */
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/* Operation control word type 1 */
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/*
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* No definitions. Written to the odd address. Bitmask for interrupts.
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* 1 = disabled.
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*/
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/* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */
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#define OCW2_L0 0x01U /* Level */
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#define OCW2_L1 0x02U
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#define OCW2_L2 0x04U
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/* 0x08 must be 0 to select OCW2 vs OCW3 */
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/* 0x10 must be 0 to select OCW2 vs ICW1 */
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#define OCW2_EOI 0x20U /* 1 = EOI */
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#define OCW2_SL 0x40U /* EOI mode */
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#define OCW2_R 0x80U /* EOI mode */
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/* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
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#define OCW3_RIS 0x01U /* 1 = read IS, 0 = read IR */
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#define OCW3_RR 0x02U /* register read */
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#define OCW3_P 0x04U /* poll mode command */
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/* 0x08 must be 1 to select OCW3 vs OCW2 */
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#define OCW3_SEL 0x08U /* must be 1 */
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/* 0x10 must be 0 to select OCW3 vs ICW1 */
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#define OCW3_SMM 0x20U /* special mode mask */
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#define OCW3_ESMM 0x40U /* enable SMM */
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#define IO_ELCR1 0x4d0U
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#define IO_ELCR2 0x4d1U
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enum vpic_trigger {
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EDGE_TRIGGER,
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LEVEL_TRIGGER
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};
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void *vpic_init(struct vm *vm);
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void vpic_cleanup(struct vm *vm);
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int vpic_assert_irq(struct vm *vm, uint32_t irq);
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int vpic_deassert_irq(struct vm *vm, uint32_t irq);
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int vpic_pulse_irq(struct vm *vm, uint32_t irq);
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void vpic_pending_intr(struct vm *vm, uint32_t *vecptr);
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void vpic_intr_accepted(struct vm *vm, uint32_t vector);
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int vpic_set_irq_trigger(struct vm *vm, uint32_t irq,
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enum vpic_trigger trigger);
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int vpic_get_irq_trigger(struct vm *vm, uint32_t irq,
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enum vpic_trigger *trigger);
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bool vpic_is_pin_mask(struct acrn_vpic *vpic, uint8_t virt_pin_arg);
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#endif /* _VPIC_H_ */
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