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59cd872858997e7c110af768f34561f016a01b74
acrn-hypervisor/hypervisor/include/arch/riscv/asm
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Yifan Liu 59cd872858 hv: riscv: Add CSR operation functions and CSR macros 
Adds csr read/write/set/clear/read_set/read_clear/swap utilities.

Also adds definitions for CSRs.

Tracked-On: #8838
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>
2025-11-04 10:59:30 +08:00
..
boot
hv: risc-v: add relocation support
2025-10-22 10:15:01 +08:00
guest
hv: riscv: Add skeleton vcpu and vm to enable RISC-V build
2025-10-30 13:30:32 +08:00
lib
hv: multi-arch add RISC-V bits library implementation
2025-09-22 10:52:06 +08:00
cpu.h
hv: riscv: add access usr memory interface
2025-10-21 14:14:55 +08:00
csr.h
hv: riscv: Add CSR operation functions and CSR macros
2025-11-04 10:59:30 +08:00
host_pm.h
hv: host_pm: Move two common APIs to common scope
2025-10-30 13:30:32 +08:00
init.h
hv: risc-v: add C entry function of BSP and APs
2025-09-15 13:12:21 +08:00
io.h
io: add risc-v mmio read and write APIs with memory order
2025-10-09 17:15:06 +08:00
irq.h
hv: riscv: irq: add interrupt initialization and handlers
2025-09-29 14:01:00 +08:00
mm_common.h
hv: riscv: add riscv memory interface
2025-10-21 14:14:55 +08:00
mmu.h
hv:riscv: add memory initizalization
2025-10-21 14:14:55 +08:00
notify.h
hv: smpcall: riscv: implement SMP call handlers
2025-09-09 16:37:04 +08:00
offset.h
hv: riscv: fix stack allocation in cpu_ctx_save/cpu_ctx_restore
2025-10-14 09:45:17 +08:00
page.h
hv: multiarch: move some function to common
2025-10-21 14:14:55 +08:00
pci_dev.h
hv: riscv: Add skeleton vcpu and vm to enable RISC-V build
2025-10-30 13:30:32 +08:00
per_cpu.h
hv: riscv: add get/set_pcpu_id and start_pcpus implementation
2025-09-23 11:30:38 +08:00
pgtable.h
hv: multiarch: add hva2hpa_early/hpa2hva_early to common
2025-10-21 14:14:55 +08:00
qemu.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
sbi.h
hv: riscv: add SBI HSM HART_START interface
2025-09-23 11:30:38 +08:00
security.h
hv: risc-v: enable stack_protector
2025-10-29 17:45:44 +08:00
timer.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
trap.h
hv: riscv: irq: add interrupt initialization and handlers
2025-09-29 14:01:00 +08:00
vm_config.h
hv/misc: vm_config: vm_config abstraction
2025-10-30 13:30:32 +08:00