Binbin Wu 5c7f120d96 hv: refine guest control register handling ... In current implemenation, cr0/cr4 host mask value are set according to the value from fixed0/fixed1 values of cr0/cr4. In fact, host mask can be set to the bits, which need to be trapped. This patch, add code to support exiting long mode in CR0 write handling. Add some check when modify CR0/CR4. - CR0_PG, CR0_PE, CR0_WP, CR0_NE are trapped for CR0. PG, PE are trapped to track vcpu mode switch. WP is trapped for info of protection when paing walk. NE is always on bit. - CR4_PSE, CR4_PAE, CR4_VMXE are trapped for CR4. PSE, PAE are trapped to track paging mode. VMXE is always on bit. - Reserved bits and always off bits are not allow to be set by guest. If guest try to set these bits when vmexit, a #GP will be injected. Signed-off-by: Binbin Wu <binbin.wu@intel.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com> Acked-by: Xu, Anthony <anthony.xu@intel.com>		2018-06-01 19:14:13 +08:00
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arch/x86	hv: refine guest control register handling	2018-06-01 19:14:13 +08:00
common	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
debug	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
lib	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
public	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
hv_debug.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
hv_lib.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
hypervisor.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00