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https://github.com/projectacrn/acrn-hypervisor.git
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2470e7f064
Tracked-On: #8805 Signed-off-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
120 lines
3.9 KiB
C
120 lines
3.9 KiB
C
/*
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* Copyright (C) 2018-2022 Intel Corporation.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <types.h>
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#include <asm/irq.h>
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#include <asm/page.h>
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#define CALL_TRACE_HIERARCHY_MAX 0x10U
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#define DUMP_STACK_SIZE 0x800U
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void asm_assert(__unused int32_t line, __unused const char *file, __unused const char *txt) {}
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static void show_host_call_trace(uint64_t stack_phy, uint64_t s0, uint16_t pcpu_id)
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{
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uint32_t i = 0U;
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uint32_t cb_hierarchy = 0U;
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uint64_t *fp = (uint64_t *)s0;
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uint64_t *sp = (uint64_t *)stack_phy;
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uint64_t dump_size = min(roundup(stack_phy, PAGE_SIZE) - stack_phy, DUMP_STACK_SIZE);
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/* TODO: pritf the delta between the actual load address and the config load address here */
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//pr_acrnlog("\r\n delta = (actual_load_address - CONFIG_HV_RAM_START) = 0x%llx\r\n", get_hv_image_delta());
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pr_acrnlog("Host Stack: CPU_ID = %hu\r\n", pcpu_id);
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for (i = 0U; i < (dump_size >> 5U); i++) {
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pr_acrnlog("addr(0x%lx) 0x%016lx 0x%016lx 0x%016lx 0x%016lx\r\n",
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(stack_phy + (i * 32U)), sp[i * 4U],
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sp[(i * 4U) + 1U], sp[(i * 4U) + 2U],
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sp[(i * 4U) + 3U]);
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}
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pr_acrnlog("\r\n");
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pr_acrnlog("Host Call Trace:\r\n");
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/* if enable compiler option(no-omit-frame-pointer) the stack layout
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* should be like this when call a function for risc-v
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*
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* | |
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* fp + 16 | last fp pointer |
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* fp + 8 | return address | push ra
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* | | sw fp s0
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*
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* rsp | |
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*
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*
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* if the address is invalid, it will cause hv page fault
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* then halt system */
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while (cb_hierarchy < CALL_TRACE_HIERARCHY_MAX) {
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pr_acrnlog("----> 0x%016lx\r\n", *(uint64_t *)(fp - 1));
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if (*fp == SP_BOTTOM_MAGIC) {
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break;
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}
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fp = (uint64_t *)(*(fp - 2));
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cb_hierarchy++;
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}
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pr_acrnlog("\r\n");
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}
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/* General purpose registers. */
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// s2; s3; s4; s5; s6; s7; s8; s9; s10; s11;
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// t3; t4; t5; t6;
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void dump_intr_excp_frame(const struct intr_excp_ctx *ctx)
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{
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pr_acrnlog("================================================");
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pr_acrnlog("================================\n");
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/* Dump host register*/
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pr_acrnlog("Host Registers:\r\n");
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pr_acrnlog("= CAUSE=0x%016llX EPC=0x%016llX\n",
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ctx->regs.cause, ctx->regs.epc);
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pr_acrnlog("= TVAL=0x%016llX STATUS=0x%016llX, SCRATCH=0x%016llX\n",
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ctx->regs.tval, ctx->regs.status, ctx->regs.scratch);
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pr_acrnlog("= RA=0x%016llX SP=0x%016llX GP=0x%016llX, TP=0x%016llX\n",
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ctx->regs.ra, ctx->regs.sp, ctx->regs.gp, ctx->regs.tp);
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/* Temporary registers */
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pr_acrnlog("= T0=0x%016llX T1=0x%016llX T2=0x%016llX\n",
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ctx->regs.t0, ctx->regs.t1, ctx->regs.t2);
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/* Callee-saved registers */
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pr_acrnlog("= S0=0x%016llX S1=0x%016llX\n",
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ctx->regs.s0, ctx->regs.s1);
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/* Argument registers */
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pr_acrnlog("= A0=0x%016llX A1=0x%016llX, A2=0x%016llX A3=0x%016llX\n",
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ctx->regs.a0, ctx->regs.a1, ctx->regs.a2, ctx->regs.a3);
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pr_acrnlog("= A4=0x%016llX A5=0x%016llX, A6=0x%016llX A7=0x%016llX\n",
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ctx->regs.a4, ctx->regs.a5, ctx->regs.a6, ctx->regs.a7);
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/* Callee-saved registers */
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pr_acrnlog("= S2=0x%016llX S3=0x%016llX, S4=0x%016llX S5=0x%016llX\n",
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ctx->regs.s2, ctx->regs.s3, ctx->regs.s4, ctx->regs.s5);
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pr_acrnlog("= S6=0x%016llX S7=0x%016llX, S8=0x%016llX S9=0x%016llX\n",
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ctx->regs.s6, ctx->regs.s7, ctx->regs.s8, ctx->regs.s9);
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pr_acrnlog("= S10=0x%016llX S11=0x%016llX\n",
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ctx->regs.s10, ctx->regs.s11);
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/* Temporary registers */
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pr_acrnlog("= T3=0x%016llX T4=0x%016llX T5=0x%016llX, T6=0x%016llX\n",
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ctx->regs.t3, ctx->regs.t4, ctx->regs.t5, ctx->regs.t6);
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pr_acrnlog("\r\n");
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pr_acrnlog("=====================================================");
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pr_acrnlog("===========================\n");
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}
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void dump_exception(const struct intr_excp_ctx *ctx, uint16_t pcpu_id)
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{
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/* Dump host context */
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dump_intr_excp_frame(ctx);
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/* Show host stack */
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show_host_call_trace(ctx->regs.sp, ctx->regs.s0, pcpu_id);
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}
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