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In almost case, vLAPIC will only be accessed by the related vCPU. There's no synchronization issue in this case. However, other vCPUs could deliver interrupts to the current vCPU, in this case, the IRR (for APICv base situation) or PIR (for APICv advanced situation) and TMR for both cases could be accessed by more than one vCPUS simultaneously. So operations on IRR or PIR should be atomical and visible to other vCPUs immediately. In another case, vLAPIC could be accessed by another vCPU when create vCPU or reset vCPU which could be supposed to be consequently. Tracked-On: #1842 Signed-off-by: Li, Fei1 <fei1.li@intel.com> |
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| acpi_parser | ||
| arch/x86 | ||
| boot | ||
| bsp/ld | ||
| common | ||
| debug | ||
| dm | ||
| hw | ||
| include | ||
| lib | ||
| pre_build | ||
| release | ||
| scenarios | ||
| scripts | ||
| Kconfig | ||
| MAINTAINERS | ||
| Makefile | ||
| README.rst | ||
ACRN Hypervisor ############### The open source `Project ACRN`_ defines a device hypervisor reference stack and an architecture for running multiple software subsystems, managed securely, on a consolidated system by means of a virtual machine manager. It also defines a reference framework implementation for virtual device emulation, called the "ACRN Device Model". The ACRN Hypervisor is a Type 1 reference hypervisor stack, running directly on the bare-metal hardware, and is suitable for a variety of IoT and embedded device solutions. The ACRN hypervisor addresses the gap that currently exists between datacenter hypervisors, and hard partitioning hypervisors. The ACRN hypervisor architecture partitions the system into different functional domains, with carefully selected guest OS sharing optimizations for IoT and embedded devices. You can find out more about Project ACRN on the `Project ACRN documentation`_ website. .. _`Project ACRN`: https://projectacrn.org .. _`ACRN Hypervisor`: https://github.com/projectacrn/acrn-hypervisor .. _`Project ACRN documentation`: https://projectacrn.github.io/