Junming Liu f2bf3d3ed1 dm:gvt:update bus0 memlimit32 value ...

Now the GVT already tries to reserve the region.
the problem is that the region should be
reflected in PCI BUS0 memlimit32 and updated to DSDT table.

As the GVT PCI bar0/2 is in reserved region
and not updated to memlimit32 in DSDT table,
the problem is triggered.

Tracked-On: projectacrn#4227

Signed-off-by: Junming Liu <junming.liu@intel.com>
Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>

2019-12-12 09:04:30 +08:00

..

pci

dm:gvt:update bus0 memlimit32 value

2019-12-12 09:04:30 +08:00

platform

dm:use acrn-dm logger function instread of fprintf

2019-11-14 15:34:04 +08:00

block_if.c

dm:use acrn-dm logger function instread of fprintf

2019-11-14 15:34:04 +08:00

uart_core.c

dm: refine assert usage

2019-06-24 11:57:05 +08:00

usb_core.c

DM USB: modify disconnecting logic to support Windows 10

2019-09-26 11:29:22 +08:00