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https://github.com/projectacrn/acrn-hypervisor.git
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7a3a539b17
internal commit: 14ac2bc2299032fa6714d1fefa7cf0987b3e3085 Signed-off-by: Eddie Dong <eddie.dong@intel.com>
95 lines
2.9 KiB
C
95 lines
2.9 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hypervisor.h>
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#include <hv_lib.h>
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#include <acrn_common.h>
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#include <hv_arch.h>
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#include <bsp_extern.h>
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#include <vtd.h>
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/* IOAPIC id */
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#define SBL_IOAPIC_ID 8
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/* IOAPIC base address */
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#define SBL_IOAPIC_ADDR 0xfec00000
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/* IOAPIC range size */
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#define SBL_IOAPIC_SIZE 0x100000
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/* Local APIC base address */
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#define SBL_LAPIC_ADDR 0xfee00000
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/* Local APIC range size */
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#define SBL_LAPIC_SIZE 0x100000
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/* Number of PCI IRQ assignments */
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#define SBL_PCI_IRQ_ASSIGNMENT_NUM 28
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#ifndef CONFIG_DMAR_PARSE_ENABLED
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static struct dmar_dev_scope default_drhd_unit_dev_scope0[] = {
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{ .bus = 0, .devfun = DEVFUN(0x2, 0), },
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};
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static struct dmar_drhd drhd_info_array[] = {
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{
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.dev_cnt = 1,
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.segment = 0,
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.flags = 0,
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.reg_base_addr = 0xFED64000,
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/* Ignore the iommu for intel graphic device since GVT-g needs
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* vtd disabled for gpu
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*/
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.ignore = true,
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.devices = default_drhd_unit_dev_scope0,
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},
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{
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/* No need to specify devices since
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* DRHD_FLAG_INCLUDE_PCI_ALL_MASK set
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*/
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.dev_cnt = 0,
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.segment = 0,
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.flags = DRHD_FLAG_INCLUDE_PCI_ALL_MASK,
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.reg_base_addr = 0xFED65000,
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.ignore = false,
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.devices = NULL,
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},
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};
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static struct dmar_info sbl_dmar_info = {
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.drhd_count = 2,
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.drhd_units = drhd_info_array,
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};
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struct dmar_info *get_dmar_info(void)
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{
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return &sbl_dmar_info;
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}
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#endif
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void init_bsp(void)
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{
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}
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