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6276763cd5784d28f57bd6d97c3f9e062bc02bfe
acrn-hypervisor/hypervisor/include/arch/riscv/asm
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Haicheng Li 6276763cd5 hv: riscv: implement cpu_ctx_save and cpu_ctx_restore 
Implement cpu_ctx_save and cpu_ctx_restore to save and restore CPU
registers around exception and interrupt handling on RISC-V.

Tracked-On: #8813
Signed-off-by: Haicheng Li <haicheng.li@intel.com>
Co-developed-by: Shiqing Gao <shiqing.gao@intel.com>
Signed-off-by: Yifan Liu <yifan1.liu@intel.com>
Signed-off-by: Shiqing Gao <shiqing.gao@intel.com>
Reviewed-by: Yifan Liu  <yifan1.liu@intel.com>
Acked-by: Wang, Yu1 <yu1.wang@intel.com>
2025-09-29 14:01:00 +08:00
..
guest
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00
lib
hv: multi-arch add RISC-V bits library implementation
2025-09-22 10:52:06 +08:00
cpu.h
hv: riscv: implement cpu_ctx_save and cpu_ctx_restore
2025-09-29 14:01:00 +08:00
init.h
hv: risc-v: add C entry function of BSP and APs
2025-09-15 13:12:21 +08:00
irq.h
…
notify.h
hv: smpcall: riscv: implement SMP call handlers
2025-09-09 16:37:04 +08:00
offset.h
hv: riscv: implement cpu_ctx_save and cpu_ctx_restore
2025-09-29 14:01:00 +08:00
page.h
enable common code compile
2025-09-19 15:04:55 +08:00
per_cpu.h
hv: riscv: add get/set_pcpu_id and start_pcpus implementation
2025-09-23 11:30:38 +08:00
pgtable.h
[FIXME] hv: riscv: add build dependencies temporarily
2025-09-23 11:30:38 +08:00
qemu.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
sbi.h
hv: riscv: add SBI HSM HART_START interface
2025-09-23 11:30:38 +08:00
security.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00
timer.h
risc-v: initial timer codes
2025-09-17 08:55:12 +08:00
vm_config.h
hv: multiarch: riscv: add dummy header for riscv
2025-09-19 15:04:55 +08:00