mirror of
https://github.com/projectacrn/acrn-hypervisor.git
synced 2026-01-04 23:24:56 +00:00
628bca5cad
In order to support platform (such as Ander Lake) which physical address width bits is 46, the current code need to reserve 2^16 PD page ((2^46) / (2^30)). This is a complete waste of memory. This patch would reserve PD page by three parts: 1. DRAM - may take PD_PAGE_NUM(CONFIG_PLATFORM_RAM_SIZE) PD pages at most; 2. low MMIO - may take PD_PAGE_NUM(MEM_1G << 2U) PD pages at most; 3. high MMIO - may takes (CONFIG_MAX_PCI_DEV_NUM * 6U) PD pages (may plus PDPT entries if its size is larger than 1GB ) at most for: (a) MMIO BAR size must be a power of 2 from 16 bytes; (b) MMIO BAR base address must be power of two in size and are aligned with its size. Tracked-On: #5929 Signed-off-by: Li Fei1 <fei1.li@intel.com>
ACRN Hypervisor ############### The open source `Project ACRN`_ defines a device hypervisor reference stack and an architecture for running multiple software subsystems, managed securely, on a consolidated system by means of a virtual machine manager. It also defines a reference framework implementation for virtual device emulation, called the "ACRN Device Model". The ACRN Hypervisor is a Type 1 reference hypervisor stack, running directly on the bare-metal hardware, and is suitable for a variety of IoT and embedded device solutions. The ACRN hypervisor addresses the gap that currently exists between datacenter hypervisors, and hard partitioning hypervisors. The ACRN hypervisor architecture partitions the system into different functional domains, with carefully selected guest OS sharing optimizations for IoT and embedded devices. You can find out more about Project ACRN on the `Project ACRN documentation`_ website. .. _`Project ACRN`: https://projectacrn.org .. _`ACRN Hypervisor`: https://github.com/projectacrn/acrn-hypervisor .. _`Project ACRN documentation`: https://projectacrn.github.io/