Wu Zhou 6a430de814 hv: remove CPU frequency control from guests ... The design of ACRN CPU performance management is to let hardware do the autonomous frequency selection(or set to a fixed value), and remove guest's ability to control CPU frequency. This patch is to remove guest's ability to control CPU frequency by removing the guests' HWP/EIST CPUIDs and blocking the related MSR accesses. Including: - Remove CPUID.06H:EAX[7..11] (HWP) - Remove CPUID.01H:ECX[7] (EIST) - Inject #GP(0) upon accesses to MSR_IA32_PM_ENABLE, MSR_IA32_HWP_CAPABILITIES, MSR_IA32_HWP_REQUEST, MSR_IA32_HWP_STATUS, MSR_IA32_HWP_INTERRUPT, MSR_IA32_HWP_REQUEST_PKG - Emulate MSR_IA32_PERF_CTL. Value written to MSR_IA32_PERF_CTL is just stored for reading. This is like how the native environment would behavior when EIST is disabled from BIOS. - Emulate MSR_IA32_PERF_STATUS by filling it with base frequency state. This is consistent with Windows, which displays current frequency as base frequency when running in VM. - Hide the IA32_MISC_ENABLE bit 16 (EIST enable) from guests. This bit is dependent to CPUID.01H:ECX[7] according to SDM. - Remove CPID.06H:ECX[0] (hardware coordination feedback) - Inject #GP(0) upon accesses to IA32_MPERF, IA32_APERF Also DM do not need to generate _PSS/_PPC for post-launched VMs anymore. This is done by letting hypercall HC_PM_GET_CPU_STATE sub command ACRN_PMCMD_GET_PX_CNT and ACRN_PMCMD_GET_PX_DATA return (-1). Tracked-On: #8168 Signed-off-by: Wu Zhou <wu.zhou@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2022-09-21 03:48:58 +08:00
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asm	hv: remove CPU frequency control from guests	2022-09-21 03:48:58 +08:00