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https://github.com/projectacrn/acrn-hypervisor.git
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062fe19800
This patch moves vmx_rdmsr_pat/vmx_wrmsr_pat from vmcs.c to vmsr.c, so that these two functions would become internal functions inside vmsr.c. This approach improves the modularity. v1 -> v2: * remove 'vmx_rdmsr_pat' * rename 'vmx_wrmsr_pat' with 'write_pat_msr' Tracked-On: #1842 Signed-off-by: Shiqing Gao <shiqing.gao@intel.com> Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
68 lines
1.7 KiB
C
68 lines
1.7 KiB
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VMCS_H_
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#define VMCS_H_
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#define VM_SUCCESS 0
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#define VM_FAIL -1
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#ifndef ASSEMBLER
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#include <types.h>
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#include <vmx.h>
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#include <vcpu.h>
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#define VMX_VMENTRY_FAIL 0x80000000U
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#define APIC_ACCESS_OFFSET 0xFFFUL /* 11:0, offset within the APIC page */
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#define APIC_ACCESS_TYPE 0xF000UL /* 15:12, access type */
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#define TYPE_LINEAR_APIC_INST_READ (0UL << 12U)
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#define TYPE_LINEAR_APIC_INST_WRITE (1UL << 12U)
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static inline uint32_t vmx_eoi_exit(uint32_t vector)
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{
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return (VMX_EOI_EXIT0_FULL + ((vector >> 6U) * 2U));
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}
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/* VM exit qulifications for APIC-access
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* Access type:
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* 0 = linear access for a data read during instruction execution
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* 1 = linear access for a data write during instruction execution
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* 2 = linear access for an instruction fetch
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* 3 = linear access (read or write) during event delivery
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* 10 = guest-physical access during event delivery
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* 15 = guest-physical access for an instructon fetch or during
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* instruction execution
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*/
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static inline uint64_t apic_access_type(uint64_t qual)
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{
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return (qual & APIC_ACCESS_TYPE);
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}
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static inline uint64_t apic_access_offset(uint64_t qual)
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{
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return (qual & APIC_ACCESS_OFFSET);
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}
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#define RFLAGS_C (1U<<0U)
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#define RFLAGS_Z (1U<<6U)
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#define RFLAGS_AC (1U<<18U)
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#define VMX_SUPPORT_UNRESTRICTED_GUEST (1U<<5U)
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void init_vmcs(struct acrn_vcpu *vcpu);
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void switch_apicv_mode_x2apic(struct acrn_vcpu *vcpu);
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static inline enum vm_cpu_mode get_vcpu_mode(const struct acrn_vcpu *vcpu)
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{
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return vcpu->arch.cpu_mode;
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}
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#endif /* ASSEMBLER */
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#endif /* VMCS_H_ */
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