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5b43521461
ACRN needs to trap the pm1a/pm1b written/read from VM0. So we could know when should we put the system to S3. We will have two path back to VM0: - S3 enter/exit sucess. Will reset VM0 and jump to VM0 wakeup vec with real mode - S3 enter/exit failed. Will return to the next instruction of pm1a/pm1b register writing. VM0 will read the pm1a/pm1b evt register to check whether it's waked up or not. Signed-off-by: Victor Sun <victor.sun@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
17 lines
412 B
C
17 lines
412 B
C
/*
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* Copyright (C) 2018 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GUEST_PM_H
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#define GUEST_PM_H
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void vm_setup_cpu_state(struct vm *vm);
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int vm_load_pm_s_state(struct vm *vm);
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int validate_pstate(struct vm *vm, uint64_t perf_ctl);
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struct cpu_cx_data* get_target_cx(struct vm *vm, uint8_t cn);
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void register_pm1ab_handler(struct vm *vm);
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#endif /* PM_H */
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