Yu Wang 6e86d4841d hv: vioapic: set remote IRR to zero once trigger mode switch to edge ... In some special scenarios, the LAPIC somehow hasn't send EOI to IOAPIC which cause the Remote IRR bit can't be clear. To clear it, some OSes will use EOI Register to clear it for 0x20 version IOAPIC, otherwise use switch Trigger Mode to Edge Sensitive to clear it. This patch emulate this IOAPIC behavior to satisfy this requirement. Signed-off-by: Yu Wang <yu1.wang@intel.com> Acked-by: Anthony Xu <anthony.xu@intel.com>		2018-08-06 12:32:35 +08:00
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x86	hv: vioapic: set remote IRR to zero once trigger mode switch to edge	2018-08-06 12:32:35 +08:00