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https://github.com/projectacrn/acrn-hypervisor.git
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cf73187528
add pgtable callbacks set_pgentry to implement arch specific set generic page table entry for any paging level, and remove x86 specific tweak_exe_right/recover_exe_right callbacks, move the logic in set_pgentry callback. remove common set_pgentry function to avoid confusing. Tracked-On: #8831 Signed-off-by: hangliu1 <hang1.liu@intel.com> Reviewed-by: Fei Li <fei1.li@intel.com> Acked-by: Wang, Yu1 <yu1.wang@intel.com>
31 lines
864 B
C
31 lines
864 B
C
/*
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* Copyright (C) 2023-2024 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef __X86_MM_COMMON_H__
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#define __X86_MM_COMMON_H__
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#include <asm/pgtable.h>
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#define PGTL3_SHIFT PML4E_SHIFT
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#define PGTL3_SIZE (1UL << PGTL3_SHIFT)
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#define PGTL3_MASK (~(PGTL3_SIZE - 1UL))
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#define PTRS_PER_PGTL3E PTRS_PER_PML4E
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#define PGTL2_SHIFT PDPTE_SHIFT
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#define PGTL2_SIZE (1UL << PGTL2_SHIFT)
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#define PGTL2_MASK (~(PGTL2_SIZE - 1UL))
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#define PTRS_PER_PGTL2E PTRS_PER_PDPTE
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#define PGTL1_SHIFT PDE_SHIFT
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#define PGTL1_SIZE (1UL << PGTL1_SHIFT)
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#define PGTL1_MASK (~(PGTL1_SIZE - 1UL))
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#define PTRS_PER_PGTL1E PTRS_PER_PDE
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#define PGTL0_SHIFT PTE_SHIFT
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#define PGTL0_SIZE (1UL << PGTL0_SHIFT)
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#define PGTL0_MASK (~(PGTL0_SIZE - 1UL))
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#define PTRS_PER_PGTL0E PTRS_PER_PTE
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#define PAGE_PFN_OFFSET 12
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#endif /*__X86_MM_COMMON_H__ */
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