Chenli Wei 72c406c2b7 misc: move the RDT interface to common library ... The current RDT class and interface was define by the clos.py which is mix get and merge RDT policy, create clos nodes. Now we need call these interface to check the CLOS IDs number after merged RDT policy, so this patch abstract the RDT interface to common and add an assert to check the CLOS IDs number. Tracked-On: #6690 Signed-off-by: Chenli Wei <chenli.wei@intel.com> Signed-off-by: Junjie Mao <junjie.mao@intel.com>		2022-06-29 13:53:42 +08:00
..
lib	misc: configurator: Add entry "None" to HV console selector	2022-05-24 17:14:38 +08:00
bdf.py	config-tools: Fix Enable SR-IOV build fail	2022-05-24 16:07:16 +08:00
board_capability.py	misc: add the define of MAX_IR_ENTRIES	2022-05-20 09:08:47 +08:00
clos.py	misc: move the RDT interface to common library	2022-06-29 13:53:42 +08:00
cpu_affinity.py	config_tools: track whether each vCPU is used for real-time or not	2022-04-21 10:08:53 +08:00
gpa.py	config-tools: extract the SSRAM area size	2022-04-18 16:47:23 +08:00
guest_flags.py	misc: set PMU_PT flag for pre-launched RTVM	2022-03-29 09:34:17 +08:00
hv_ram.py	misc: modify the HV start address	2022-06-29 13:53:42 +08:00
intx.py	misc: fix the conflict between S5 and LPC	2022-06-29 13:53:42 +08:00
main.py	misc: fix the issue of create hv node	2022-04-28 13:42:54 +08:00
memory_allocator.py	config-tools:refine memory allocation for vm	2022-06-29 13:53:42 +08:00
pio.py	Remove "All rights reserved" string headers	2022-04-06 13:21:02 +08:00
s5_vuart.py	misc: add processing for Console vUART is None	2022-06-29 13:53:42 +08:00