Li Fei1 77e64f6092 hv: tlb: wrap common APIs ...

Wrap two common TLB APIs: flush_tlb and flush_tlb_range.

Tracked-On: #5830
Signed-off-by: Li Fei1 <fei1.li@intel.com>

2021-05-14 09:18:00 +08:00

..

arch/x86/asm

hv: tlb: wrap common APIs

2021-05-14 09:18:00 +08:00

common

hv: hypercalls: refactor permission-checking and dispatching logic

2021-05-12 13:43:41 +08:00

debug

hv: mod: do not use explicit arch name when including headers

2021-05-08 11:15:46 +08:00

dm

hv: mod: do not use explicit arch name when including headers

2021-05-08 11:15:46 +08:00

hw

HV: deny HV owned PCI bar access from SOS

2021-02-03 14:01:23 +08:00

lib

hv: bugfix in min() and max() MACROs

2021-04-23 09:58:21 +08:00

public

config-tools: add NVMX_ENABLED feature and GUEST_FLAG_NVMX_ENABLED flag

2021-05-13 16:16:30 +08:00