Chenli Wei 7965b66629 misc: modify the vUART index order and irq ...

There were some legacy logic of the current code, the PCI vUART index
in the launch script have not count the vUART of S5 and life_mngr_win
use the COM2 as default vUART.

This patch change the vUART index and irq to adapt above logic and all
of these legacy code will be refine next version.

Tracked-On: #6690
Signed-off-by: Chenli Wei <chenli.wei@intel.com>

2022-06-29 13:53:42 +08:00

..

lib

misc: configurator: Add entry "None" to HV console selector

2022-05-24 17:14:38 +08:00

bdf.py

config-tools: Fix Enable SR-IOV build fail

2022-05-24 16:07:16 +08:00

board_capability.py

misc: add the define of MAX_IR_ENTRIES

2022-05-20 09:08:47 +08:00

clos.py

misc: move the RDT interface to common library

2022-06-29 13:53:42 +08:00

cpu_affinity.py

config_tools: track whether each vCPU is used for real-time or not

2022-04-21 10:08:53 +08:00

gpa.py

config-tools: extract the SSRAM area size

2022-04-18 16:47:23 +08:00

guest_flags.py

…

hv_ram.py

misc: modify the HV start address

2022-06-29 13:53:42 +08:00

intx.py

misc: modify the vUART index order and irq

2022-06-29 13:53:42 +08:00

main.py

misc: fix the issue of create hv node

2022-04-28 13:42:54 +08:00

memory_allocator.py

config_tools: update the hugepage algorithm

2022-06-29 13:53:42 +08:00

pio.py

…

s5_vuart.py

misc: modify the vUART index order and irq

2022-06-29 13:53:42 +08:00