Yonghua Huang 7aae9807b3 dm: add RTCT SSRAM entries from vSSRAM buffers ...

add all L2 & L3 cache buffers to RTCT entries:
   - SSRAM WAY_MASK entry, cache ways bitmask indicates
     the cache ways used by specific cache buffer.

   -  SSRAM region entry, support format V2 only.

Tracked-On: #7010
Signed-off-by: Yonghua Huang <yonghua.huang@intel.com>
Acked-by: Wang Yu1 <yu1.wang@intel.com>

2022-01-10 13:34:27 +08:00

..

mmio

dm: Fix potential overflow bug

2021-11-04 10:34:13 +08:00

pci

dm: remove some dynamic parameters from acrn-dm usage

2021-12-29 14:25:50 +08:00

platform

dm: add RTCT SSRAM entries from vSSRAM buffers

2022-01-10 13:34:27 +08:00

block_if.c

dm: blockif: Convert print output to acrn-dm logger

2020-09-10 09:33:25 +08:00

uart_core.c

ACRN: misc: Unify terminology for sos/uos rin macro

2021-11-02 10:00:55 +08:00

usb_core.c

DM USB: modify disconnecting logic to support Windows 10

2019-09-26 11:29:22 +08:00