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https://github.com/projectacrn/acrn-hypervisor.git
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b10b5658bd
With shadow EPT, the hypervisor walks through guest EPT table:
* If the entry is not present in guest EPT, ACRN injects EPT_VIOLATION
to L1 VM and resumes to L1 VM.
* If the entry is present in guest EPT, do the EPT_MISCONFIG check.
Inject EPT_MISCONFIG to L1 VM if the check failed.
* If the entry is present in guest EPT, do permission check.
Reflect EPT_VIOLATION to L1 VM if the check failed.
* If the entry is present in guest EPT but shadow EPT entry is not
present, create the shadow entry and resumes to L2 VM.
* If the entry is present in guest EPT but the GPA in the entry is
invalid, injects EPT_VIOLATION to L1 VM and resumes L1 VM.
Tracked-On: #5923
Signed-off-by: Sainath Grandhi <sainath.grandhi@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
Signed-off-by: Shuo A Liu <shuo.a.liu@intel.com>
Reviewed-by: Jason Chen CJ <jason.cj.chen@intel.com>
Acked-by: Eddie Dong <eddie.dong@intel.com>
52 lines
1.9 KiB
C
52 lines
1.9 KiB
C
/*
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* Copyright (C) 2021 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef VEPT_H
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#define VEPT_H
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#ifdef CONFIG_NVMX_ENABLED
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#define RESERVED_BITS(start, end) (((1UL << (end - start + 1)) - 1) << start)
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#define IA32E_PML4E_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(3U, 7U) | RESERVED_BITS(phy_addr_width, 51U))
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#define IA32E_PDPTE_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(3U, 6U) | RESERVED_BITS(phy_addr_width, 51U))
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#define IA32E_PDPTE_LEAF_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(12U,29U)| RESERVED_BITS(phy_addr_width, 51U))
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#define IA32E_PDE_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(3U, 6U) | RESERVED_BITS(phy_addr_width, 51U))
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#define IA32E_PDE_LEAF_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(12U,20U)| RESERVED_BITS(phy_addr_width, 51U))
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#define IA32E_PTE_RESERVED_BITS(phy_addr_width) (RESERVED_BITS(phy_addr_width, 51U))
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#define PAGING_ENTRY_SHIFT(lvl) ((IA32E_PT - (lvl)) * 9U + PTE_SHIFT)
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#define PAGING_ENTRY_OFFSET(addr, lvl) (((addr) >> PAGING_ENTRY_SHIFT(lvl)) & (PTRS_PER_PTE - 1UL))
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/*
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* A descriptor to store info of nested EPT
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*/
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struct nept_desc {
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/*
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* A shadow EPTP.
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* The format is same with 'EPT pointer' in VMCS.
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* Its PML4 address field is a HVA of the hypervisor.
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*/
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uint64_t shadow_eptp;
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/*
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* An guest EPTP configured by L1 VM.
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* The format is same with 'EPT pointer' in VMCS.
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* Its PML4 address field is a GPA of the L1 VM.
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*/
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uint64_t guest_eptp;
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uint32_t ref_count;
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};
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void reserve_buffer_for_sept_pages(void);
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void init_vept(void);
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uint64_t get_shadow_eptp(uint64_t guest_eptp);
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struct nept_desc *get_nept_desc(uint64_t guest_eptp);
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void put_nept_desc(uint64_t guest_eptp);
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bool handle_l2_ept_violation(struct acrn_vcpu *vcpu);
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int32_t invept_vmexit_handler(struct acrn_vcpu *vcpu);
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#else
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static inline void reserve_buffer_for_sept_pages(void) {};
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#endif /* CONFIG_NVMX_ENABLED */
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#endif /* VEPT_H */
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