Tao Yuhong 8360c3dfe6 HV: enable #GP for UC lock ... For an atomic operation using bus locking, it would generate LOCK# bus signal, if it has Non-WB memory operand. This is an UC lock. It will ruin the RT behavior of the system. If MSR_IA32_CORE_CAPABILITIES[bit4] is 1, then CPU can trigger #GP for instructions which cause UC lock. This feature is controlled by MSR_TEST_CTL[bit28]. This patch enables #GP for guest UC lock. Tracked-On: #6299 Signed-off-by: Tao Yuhong <yuhong.tao@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2021-07-21 11:25:47 +08:00
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x86	HV: enable #GP for UC lock	2021-07-21 11:25:47 +08:00