Zheng, Gen 20c80ea72a HV: bug fix on emulating msi message from guest ... Current code has a mistake associating destination with redirectionhint. So just use the destination mode to work out destination mode. When injecting the msi interrupt to vcpu in hypervisor layer, current code ingnores the redirection hint(RH) bit of msi address message from guest, and just use the destination mode and destination ID. So correctly before injecting, check the RH bit, if set, choose the vcpu that has lowest priority to inject msi. Signed-off-by: Zheng, Gen <gen.zheng@intel.com> Reviewed-by: Zhao, Yakui <yakui.zhao@intel.com> Reviewed-by: Yin, Fengwei <fengwei.yin@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>		2018-07-19 11:09:09 +08:00
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guest_pm.h	hv: trap vm0 write/read pm1a/pm1b registers	2018-06-29 00:50:01 +08:00
guest.h	HV: handle integral issue report by MISRA-C	2018-07-16 16:24:29 +08:00
ucode.h	license: Replace license text with SPDX tag	2018-06-01 10:43:06 +08:00
vcpu.h	HV:treewide:Add exec_vmread32 and exec_vmwrite32 functions	2018-07-18 12:31:42 +08:00
vioapic.h	HV: vioapic: cleaning up integral-type-related violations	2018-07-17 15:37:45 +08:00
vlapic.h	HV: bug fix on emulating msi message from guest	2018-07-19 11:09:09 +08:00
vm.h	HV:transfer vmid's type to uint16_t	2018-07-13 14:13:38 +08:00
vpic.h	HV: irq: convert hexadecimals used in bitops to unsigned	2018-06-21 13:12:39 +08:00