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There can be times when user unknowinlgy enables CONFIG_CAT_ENBALED SW flag, but the hardware might not support L3 or L2 CAT. In such case software can end up writing to the CAT MSRs which can cause undefined results. The patch fixes the issue by enabling CAT only when both HW as well software via the CONFIG_CAT_ENABLED supports CAT. The patch also address typo with "clos2prq_msr" function name. It should be "clos2pqr_msr" instead. PQR stands for platform qos register. Tracked-On: #3715 Signed-off-by: Vijay Dhanraj <vijay.dhanraj@intel.com> Acked-by: Eddie Dong <eddie.dong@intel.com>
34 lines
811 B
C
34 lines
811 B
C
/*
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* Copyright (C) 2020 Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef RDT_H
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#define RDT_H
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/* The intel Resource Director Tech(RDT) based Cache Allocation Tech support */
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struct cat_hw_info {
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bool enabled; /* If L2/L3 CAT enabled */
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uint32_t bitmask; /* Used by other entities */
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uint16_t cbm_len; /* Length of Cache mask in bits */
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uint16_t clos_max; /* Maximum CLOS supported, the number of cache masks */
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uint32_t res_id;
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};
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extern struct cat_hw_info cat_cap_info;
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extern const uint16_t hv_clos;
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extern uint16_t platform_clos_num;
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void setup_clos(uint16_t pcpu_id);
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#define CAT_RESID_L3 1U
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#define CAT_RESID_L2 2U
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int32_t init_cat_cap_info(void);
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uint64_t clos2pqr_msr(uint16_t clos);
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bool is_platform_rdt_capable(void);
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#endif /* RDT_H */
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